TSB81BA3IPFPEP datasheet(39/61 Pages) TI1

39 / 61 page

TSB81BA3D, TSB81BA3DI

IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS559E − DECEMBER 2002 − REVISED JUNE 2006

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION (1394a−2000 INTERFACE)

interface reset and disable (continued)

The LLC requests that the interface be reset by deasserting the LPS signal and terminating all bus and request

activity. When the PHY observes that LPS has been deasserted for TLPS_RESET, it resets the interface. When

the interface is in the reset state, the PHY sets its CTL and D outputs in the logic 0 state and ignores any activity

on the LREQ signal. Figure 17 shows the timing for interface reset.

PCLK

(a)

(c)

(b)

CTL0, CTL1

D0 − D7

LREQ

LPS

(d)

TLPS_RESET

TRESTORE

Figure 17. Interface Reset

The sequence of events for resetting the PHY-LLC interface is as follows:

(a) Normal operation. Interface is operating normally, with LPS asserted, PCLK active, status and packet data

reception and transmission via the CTL and D lines, and request activity via the LREQ line. In the above

diagram, the LPS signal is shown as a nonpulsed level signal. However, it is permissible to use a pulsed

signal for LPS in a direct connection between the PHY and LLC; a pulsed signal is required when using an

isolation barrier.

(b) LPS deasserted. The LLC deasserts the LPS signal and, within 1.0

μs, terminates any request or interface

bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.

bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state.

(d) Interface restored. After the minimum TRESTORE time, the LLC may again assert LPS active. When LPS

is asserted, the interface is initialized as described below.

If the LLC continues to keep the LPS signal deasserted, it then requests that the interface be disabled. The PHY

disables the interface when it observes that LPS has been deasserted for TLPS_DISABLE. When the interface

is disabled, the PHY sets its CTL and D outputs as stated above for interface reset, but also stops PCLK activity.

The interface is also placed into the disabled condition upon a hardware reset of the PHY. Figure 18 shows the

timing for the interface disable.

When the interface is disabled, the PHY enters a low-power state if none of its ports are active.

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