LPC2194 datasheet(23/33 Pages) PHILIPS

23 / 33 page

Philips Semiconductors

LPC2194

Single-chip 16/32-bit microcontrollers

Preliminary data

Rev. 01 — 06 February 2004

23 of 33

9397 750 12757

fourth of the processor clock rate. The default condition at reset is for the VPB bus to

run at one quarter of the CPU clock. The second purpose of the VPB Divider is to

allow power savings when an application does not require any peripherals to run at

the full processor rate. Because the VPB Divider is connected to the PLL output, the

PLL remains active (if it was running) during Idle mode.

6.21 Emulation and debugging

The LPC2194 supports emulation and debugging via a JTAG serial port. A trace port

allows tracing program execution. Debugging and trace functions are multiplexed only

with GPIOs on Port 1. This means that all communication, timer and interface

peripherals residing on Port 0 are available during the development and debugging

phase as they are when the application is run in the embedded system itself.

6.21.1

Embedded ICE™

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging

of the target system requires a host computer running the debugger software and an

EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the

Remote Debug Protocol commands to the JTAG data needed to access the ARM

core.

The ARM core has a Debug Communication Channel function built-in. The debug

communication channel allows a program running on the target to communicate with

the host debugger or another separate host without stopping the program ﬂow or

even entering the debug state. The debug communication channel is accessed as a

co-processor 14 by the program running on the ARM7TDMI-S core. The debug

communication channel allows the JTAG port to be used for sending and receiving

data without affecting the normal program ﬂow. The debug communication channel

data and control registers are mapped in to addresses in the EmbeddedICE™ logic.

6.21.2

Embedded trace

Since the LPC2194 has signiﬁcant amounts of on-chip memory, it is not possible to

determine how the processor core is operating simply by observing the external pins.

The Embedded Trace Macrocell provides real-time trace capability for deeply

embedded processor cores. It outputs information about processor execution to the

trace port.

The ETM is connected directly to the ARM core and not to the main AMBA system

bus. It compresses the trace information and exports it through a narrow trace port.

An external trace port analyzer must capture the trace information under software

debugger control. Instruction trace (or PC trace) shows the ﬂow of execution of the

processor and provides a list of all the instructions that were executed. Instruction

trace is signiﬁcantly compressed by only broadcasting branch addresses as well as a

set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace

information generation can be controlled by selecting the trigger resource. Trigger

resources include address comparators, counters and sequencers. Since trace

information is compressed the software debugger requires a static image of the code

being executed. Self-modifying code can not be traced because of this restriction.

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