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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ASX340AT датащи(PDF) 39 Page - ON Semiconductor |
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ASX340AT датащи(HTML) 39 Page - ON Semiconductor |
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39 / 54 page  ASX340AT www.onsemi.com 39 NOTE: All I/O circuitry shown above is for reference only. The actual implementation may be different. Figure 39. NTSC Block Pad VDD_DAC GND Pad Pad ESD ESD DAC_REF ESD DAC_POS DAC_NEG NTSC Block Resistor 2.35 kW Figure 40. Serial interface Pad Transmitter GND Receiver VDD_I0 SDATA Input/output Pad I/O Timing Digital Output By default, the ASX340AT launches pixel data, FV, and LV synchronously with the falling edge of PIXCLK. The expectation is that the user captures data, FV, and LV using the rising edge of PIXCLK. The timing diagram is shown in. As an option, the polarity of the PIXCLK can be inverted from the default by programming R0x0016[14]. EXTCLK PIXCLK DOUT [7:0] FRAME_VALID LINE_VALID t pixclkf_dout t pixclkf_fvlv Input Output Output Output t fvlv_su t fvlv_ho t dout_ho t dout_su t extclk_period Figure 41. Digital Output I/O Timing |
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