AR0230CS datasheet(21/33 Pages) ONSEMI

21 / 33 page

AR0230CS/D Rev. 9, 6/16 EN

©Semiconductor Components Industries, LLC,2016.

AR0230CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor

Electrical Specifications

Notes:

1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.

2. Two-wire control is I2C-compatible.

3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.

4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the

undefined region of the falling edge of SCLK.

5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of

the SCLK signal.

6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement

tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch

the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it

must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according

to the Standard-mode I2C-bus specification) before the SCLK line is released.

7. Cb = total capacitance of one bus line in pF.

I/O Timing

By default, the AR0230CS launches pixel data, FV, and LV with the falling edge of PIXCLK.

The expectation is that the user captures DOUT[11:0], FV, and LV using the rising edge of

PIXCLK.

See Figure 10 below and Table 6 on page 22 for I/O timing (AC) characteristics.

Figure 10:

I/O Timing Diagram

Serial interface input pin capacitance

CIN_SI

3.3

SDATA max load capacitance

CLOAD_SD

SDATA pull-up resistor

RSD

1.5

4.7

1.5

4.7

K

Table 5:

Two-Wire Serial Bus Characteristics (continued)

fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; T

A = 25°C

Parameter

Symbol

Standard Mode

Fast Mode

Unit

Min

Max

Min

Max

Data[11:0]

LINE_VALID/

PIXCLK

EXTCLK

tEXTCLK

FRAME_VALID leads LINE_VALID by 6 PIXCLKs.

FRAME_VALID trails

LINE_VALID by 6 PIXCLKs.

tPLH

tPFH

tPFL

tPLL

tPD

Pxl _0

Pxl _1

Pxl _2

Pxl _n

90%

10%

tRP

tFP

90%

10%

FRAME_VALID

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