AR0141CS datasheet(59/64 Pages) ONSEMI

59 / 64 page

AR0141CS/D Rev. 6, 4/16 EN

©Semiconductor Components Industries, LLC, 2016.

AR0141CS: 1/4-Inch Digital Image Sensor

Electrical Specifications

Note:

The Clock DLL Steps 6 and 7 are not recommended by ON Semiconductor for the AR0141CS.

Note:

The Data DLL Steps 3, 5, and 7 are not recommended by ON Semiconductor for the AR0141CS.

Power-Up Sequence

The recommended power-up sequence for the AR0141CS is shown in Figure 49. The

available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have

the separation specified below.

1. Turn on VDD_PLL power supply.

2. After 100s, turn on VAA and VAA_PIX power supply.

3. After 100s, turn on VDD_IO power supply.

4. After 100s, turn on VDD power supply.

5. After 100s, turn on VDD_SLVS power supply.

6. After the last power supply is stable, enable EXTCLK.

7. Assert RESET_BAR for at least 1ms. The parallel interface will be tri-stated during this

time.

8. Wait 1800 EXTCLKs for internal initialization into software standby.

9. Initiate load of OTPM data by setting R0x304A=0x0010.

10. Wait for 185135 EXTCLKs for a full OTPM loading.

11. Configure PLL, output, and image settings to desired values.

12. Wait 1ms for the PLL to lock.

13. Set streaming mode (R0x301A[2] = 1).

Table 34:

Clock DLL Steps

Measurement Conditions: VDD_HiSPi = 1.8V;VDD_HiSPi_TX = 0.8V; Data DLL set to 0

Clock DLL Step

Step

Delay at 660 Mbps

0.25

0.375

0.5

0.625

0.75

Eye_opening at 660 Mbps

0.85

0.78

0.71

0.69

Table 35:

Data DLL Steps

Measurement Conditions: VDD_HiSPi = 1.8V;VDD_HiSPi_TX = 0.8V; Clock DLL set to 0

Data DLL Step

Step

Delay at 660 Mbps

0.25

0.375

0.625

0.875

Eye opening at 660 Mbps

0.79

0.84

0.71

0.61

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