DP7172 datasheet(4/11 Pages) COPAL

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DP7172

Table 4. ELECTRICAL CHARACTERISTICS: 50 k

and 100 k

Versions (continued)

VDD =5V 10%, or 3 V 10%; VA =VDD; VB = 0 V; –40 C<TA < +85 C; unless otherwise noted.

Parameter

Unit

Max

Typ

(Note 2)

Min

Symbol

Test Conditions

DYNAMIC CHARACTERISTICS (Notes 7 and 9)

Bandwidth –3 dB

RAB =50k / 100 k , Code = 0x80

100/40

kHz

Total Harmonic Distortion

VA =1 V rms, VB =0V,

f = 1 kHz, RAB =10k

THDW

0.05

VW Settling Time (50 k /100 k )

VA =5V, VB =0V, 1 LSB error band

2. Typical specifications represent average readings at +25 C and VDD =5V.

3. Resistor position nonlinearity error R INL is the deviation from an ideal value measured between the maximum resistance and the minim-

um resistance wiper positions. R DNL measures the relative step change from ideal between successive tap positions. Parts are guaran-

teed monotonic.

4. VAB =VDD, Wiper (VW) = no connect.

5. INL and DNL are measured at VW with the DP configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD

and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.

6. Resistor terminals A, B, W have no limitations on polarity with respect to each other.

7. Guaranteed by design and not subject to production test.

8. PDISS is calculated from (IDD xVDD). CMOS logic level inputs result in minimum power dissipation.

9. All dynamic characteristics use VDD =5V.

Table 5. TIMING CHARACTERISTICS: 50 k

and 100 k

Versions

VDD =5V

10%, or 3 V

10%; VA =VDD; VB = 0 V; –40 C<TA < +85 C; unless otherwise noted.

Parameter

Test Conditions

Symbol

Min

Typ

(Note 10)

Max

Unit

SPI INTERFACE TIMING CHARACTERISTICS (Notes 11 and 12) (Specifications Apply to All Parts)

Clock Frequency

fCLK

MHz

Input Clock Pulse width

Clock level high or low

tCH, tCL

Data Setup Time

tDS

Data Hold Time

tDH

CS Setup Time

TCSS

CS High Pulse Width

TCSW

CLK Fall to CS Fall Hold Time

TCSH0

CLK Fall to CS Rise Hold Time

TCSH1

CS Rise to Clock Rise Setup

TCS1

10. Typical specifications represent average readings at +25 C and VDD =5V.

11. Guaranteed by design and not subject to production test.

12. See timing diagram for location of measured values. All input control voltages are specified with tR =tF = 2 ns (10% to 90% of 3 V) and timed

from a voltage level of 1.5 V.

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