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DP7172 датащи(PDF) 3 Page - Copal Electronics |
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DP7172 датащи(HTML) 3 Page - Copal Electronics |
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3 / 11 page ![]() DP7172 3 Table 4. ELECTRICAL CHARACTERISTICS: 50 k and 100 k Versions VDD =5V 10%, or 3 V 10%; VA =VDD; VB = 0 V; –40 C<TA < +85 C; unless otherwise noted. Parameter Test Conditions Symbol Min Typ (Note 2) Max Unit DC CHARACTERISTICS — RHEOSTAT MODE Resistor Differential Nonlinearity (Note 3) RWB, VA = no connection R DNL 1 0.1 +1 LSB Resistor Integral Nonlinearity (Note 3) RWB, VA = no connection R INL 2 0.4 +2 LSB Nominal Resistor Tolerance (Note 4) TA =25 C RAB 20 +20 % Resistance Temperature Coefficient VAB =VDD, Wiper = no connection RAB/ T 100 ppm/ C Wiper Resistance VDD =5V RW 50 120 VDD =3V 100 250 DC CHARACTERISTICS — POTENTIOMETER DIVIDER MODE Resolution N 8 Bits Differential Nonlinearity (Note 5) DNL 1 0.1 +1 LSB Integral Nonlinearity (Note 5) INL 1 0.4 +1 LSB Voltage Divider Temperature Coefficient Code = 0x80 VW/ T 100 ppm/ C Full Scale Error Code = 0xFF VWFSE 3 1 0 LSB Zero Scale Error Code = 0x00 VWZSE 0 1 3 LSB RESISTOR TERMINALS Voltage Range (Note 6) VA,B,W GND VDD V Capacitance (Note 7) A, B f = 1 MHz, measured to GND, Code = 0 x 80 CA,B 45 pF Capacitance (Note 7) W f = 1 MHz, measured to GND, Code = 0 x 80 CW 60 pF Common Mode Leakage (Note 7) VA =VB =VDD/2 ICM 1 nA DIGITAL INPUTS Input Logic High VDD =5V VIH 0.7 x VDD V Input Logic Low VDD =5V VIL 0.3VDD V Input Logic High VDD =3V VIH 0.7 x VDD V Input Logic Low VDD =3V VIL 0.3VDD V Input Current VIN =0Vor5V IIL 1 A Input Capacitance (Note 7) CIL 5 pF POWER SUPPLIES Power Supply Range VDD RANGE 2.7 5.5 V Supply Current VIH =5VorVIL =0V IDD 0.3 2 A Power Dissipation (Note 8) VIH =5VorVIL =0V, VDD =5V PDISS 0.2 mW Power Supply Sensitivity VDD =+5V 10%, Code = Midscale PSS 0.05 %/% 2. Typical specifications represent average readings at +25 C and VDD =5V. 3. Resistor position nonlinearity error R INL is the deviation from an ideal value measured between the maximum resistance and the minim- um resistance wiper positions. R DNL measures the relative step change from ideal between successive tap positions. Parts are guaran- teed monotonic. 4. VAB =VDD, Wiper (VW) = no connect. 5. INL and DNL are measured at VW with the DP configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 6. Resistor terminals A, B, W have no limitations on polarity with respect to each other. 7. Guaranteed by design and not subject to production test. 8. PDISS is calculated from (IDD xVDD). CMOS logic level inputs result in minimum power dissipation. 9. All dynamic characteristics use VDD =5V. |
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