DM6381F datasheet(24/40 Pages) ETC

24 / 40 page

DM336P

V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set

Final

Version: DM336P-DS-F02

August 15, 2000

DM6381/82 Pin Description

Pin No.

Pin Name

I/O

Description

RD_SP2

Data Input Pin Of Serial Port 2:

The serial data is sampled at the falling edge of the SCLK. The

MSB is coming immediately after falling of FR_SP2 signal.

FR_SP2

I/O

Frame Signal For Serial Port 2:

This pin keeps at the low state normally and changes it's state

according to the rising edge of the SCLK clock. A high to low

transition initiates a data transfer.

AVDD

Analog Power For PLL Circuit

4OSCO

Oscillator Output Pin

5OSCI

Oscillator Input Pin:

A 40.32MHz crystal and feedback resister should be connected

between OCSI and OSCO.

6AGND

Analog Ground For PLL Circuit

TXDCLK

Transmit Data Rate Clock:

This pin is used as reference clock of TXD pin.

8, 29, 60, 68, 71,

84, 94, 95

DGND

Digital Ground

RXDCLK

Receive Data Rate Clock:

This pin is used as reference clock of RXD pin.

CODEC_CLK

20.16MHz Clock Output For DM6380 Chip

RXD

Modem Received Data

Shifted out to the EIA port through this pin according to the rising

edge of RXDCLK.

12, 42, 57, 90, 93

VDD

Digital Power

TXD

Modem Transmit Data

Shifted into DM6381/DM6382 from EIA port through this pin at

the rising edge of TXDCLK.

/URD

Read Indication Of Dual Port RAM, low active.

/UWR

Write Indication Of Dual Port RAM, low active.

16 - 19

UAR3 - UAR0

Dual Port RAM Address Bus Input

This address bus can access 16 bytes dual port RAM.

/UCS

Dual Port RAM Chip Select Pin, low active.

21 - 28

UD0 - UD7

I/O

Data Bus Of The Dual Port RAM

MSCLK

Clock Output Pin For DM6383

The frequency of this clock can be programmed to be either

22.43MHz or 44.87MHz.

P0.F

Output Port Bit F

P0.E

Output Port Bit E

P0.D

Output Port Bit D

P0.C

Output Port Bit C

35 - 41, 43 - 56,

58, 59, 61 - 67,

70, 72, 77 - 83,

85 - 89

No Connection

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