BQ76PL455APFCR datasheet(39/125 Pages) TI1

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SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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7.3.12.6.1

Checksum Testing

Each of the checksums (TI, USER spaces) has a test mode that causes each input bit in the checksum

calculation (that is, the register bits that are part of the checksum calculation) to flip twice (once per clock) and

the TEST_CSUM register contains the count for the number of toggles on the checksums fault output. This helps

to ensure that the background checksum testing described previously correctly discovers any bit that might be in

the wrong state.

The user's firmware, usually as a part of self-testing and validation, can initiate the tests. The

TESTCTRL[CKSUM_TEST_RUN] bits are set to begin the test on either the TI or USER space registers. See

TESTCTRL 0x20–21 (32–33) Test Control for details of the bit settings.

NOTE

Other faults may be set in the process of running this procedure, but ignore those.

7.3.12.6.1.1

Computing User Checksum

The user checksum is a 32-bit value computed using all the data values in the user data space. The computation

is a simple 32 bit add of registers and constants concatenated into 32-bit values. The computation, shown below,

consists of the data at the address specified or 0:

cust_cksum_calc =

{0, 0, 0, a3} +

{a4, a5, a6, a7} +

{0, 0, a10, a11} +

{0, a13, a14, a15} +

{a16, a17, a18, a19} +

{a20, a21, 0, 0} +

{0, 0, a30, a31}+

{0, 0, a34, a35}+

{a36, a37, 0, 0} +

{a40, 0, 0, 0}+

{0, 0,a50, a51}+

{a52, a53, a54, a55} +

{0, a61, a62, a63} +

{a64, a65, a66, a67} +

{a68, 0, 0, 0}+

{a104, a105, a106, a107} +

{a108, 0, a110, a111} +

{a120, a121, a122, a123} +

{0, a125, 0, 0}+

{a140, a141, a142, a143} +

{a144, a145, a146, a147} +

{a148, a149, a150, a151} +

{a152, a153, a154, a155} +

{a156, a157, a158, a159} +

{a160, a161, a162, a163} +

{a164, a165, a166, a167} +

{a168, a169, a170, a171} +

{a172, a173, a174, a175} +

{a176, a177, 0, 0} +

{a200, a201, a202, a203} +

{a204, a205, a206, a207} +

{0, 0, a210, a211} +

{a212, a213, a214, a215} +

{a216, a217, a218, a219} +

{a220, a221, a222, a223} +

{a224, a225, a226, a227};

NOTE

the

example

code,

refers

address

number. For example: a3 =

7.3.12.7 AUXn OV/UV Threshold Faults

The AUXn input pins can trigger a fault indication. The OV and UV thresholds for each AUXn input can be set

separately in the AUXn_OV and AUXn_UV registers. The result of each AUXn channel conversion is compared

to these values. When the threshold is exceeded (less-than AUXn_UV, greater-than AUXn[OV]), the FAULT_N

and FAULTL pins are asserted, if enabled. To stop unwanted FAULT pin assertions from one or more channels

(but other channels are desired), set the threshold voltage settings for the undesired channels to their minimum

and maximum values or only convert the desired channels.

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