BQ76PL455APFCR datasheet(21/125 Pages) TI1

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bq76PL455A

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SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

Product Folder Links: bq76PL455A

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Feature Description (continued)

(1)

Choose this value with respect to the locally supplied maximum-cell voltage and derate appropriately for operating conditions and

temperature.

(2)

Derate this value appropriately for operating conditions and temperature.

NOTE

V5VAO can only supply enough power to meet internal IC requirements; it should not

connect to external circuitry.

7.3.1.1.4

VP Regulated Output

The bq76PL455A power comes directly from the cells to which it is connected. Current draw is from the top and

bottom of the n-cell battery assembly, so that current through each cell is the same. An integrated linear

regulator utilizes an external NPN transistor (Zetex ZXTN4004K or similar) to generate a nominal 5.3-V rail on

pin VP. VP is both a power input and the sense node for this supply. The NPNB pin controls the external NPN

transistor of the regulator. A capacitor or resistor-capacitor combination must connect externally from VP to GND,

see Pin Configuration and Functions for details. VP must connect externally to VDIG and can optionally connect

to VIO. Both of these connections are through series 1-

Ω resistors and separately decoupled. This regulator is

OFF in SHUTDOWN mode.

Table 1. Recommended NPN Transistor Characteristics

PARAMETER

DESCRIPTION

TEST CONDITION

TYPICAL VALUE

UNIT

BVCEO

Collector-Emitter voltage(1)

100

Beta β

Gain

at 5 mA

> 100

CCB

Collector-Base capacitance

≤ 35

Power handling(2)

See the following text for

collector resistor details.

500

Collector current rating

> 100

Add a collector resistor between the NPN collector and the TOP pin to reduce power dissipation in the NPN

under normal and system fault conditions. The value of this resistor is chosen based on the minimum battery-

stack voltage, the bq76PL455A VP/VDIG total load current, and the load current of any external I/O circuitry

powered directly or indirectly by VP/VDIG. Also, the recommendation is to add a 1-µF decoupling capacitor

directly from the collector to AGND.

7.3.1.1.5

VDIG Power Input

VDIG is the digital voltage supply input. Always connect it to the VP pin, which normally receives power from the

NPN. Optionally, an external supply may drive VDIG, but still must be connected to VP. This applies in all

operating modes. The VDIG source is from VP through a 1-

Ω resistor. Decouple VDIG with a separate capacitor

at the pin.

7.3.1.1.6

VDD18 Regulator

A provided internal regulator generates a 1.8-V digital supply for internal device use only. The 1.8-V supply does

not require an external capacitor, and there is no pin or external connection. Faults on VDD18 that cause the

voltage to drop below its regulation may cause UART communication errors. If the fault is caused by LDO_TEST,

reset or shutdown/wakeup the device to regain functionality.

7.3.1.1.7

VIO Power Input

VIO is the voltage supply input used to power the digital I/O pins TX, RX, FAULT_N, and GPIOn. VIO may

connect to an externally regulated-supply rail, which is common to an I/O device such as a microcontroller.

Alternately, the source for VIO may be from VP through a 1-

Ω resistor. Decouple VIO with a separate capacitor

at the pin.

If VIO does not have power, the part holds in reset and enters shutdown after a short delay. This gives a very

good

reset

mechanism

for

non-stacked

systems.

Upon

power

from

SHUTDOWN,

the

SHDN_STS[GTSD_PD_STAT] bit will be set. This flag bit is the logical <OR> of this condition or triggering the

thermal shutdown of the digital die in a die overtemperature situation.

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