DA9211 datasheet(36/74 Pages) DIALOG

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DA9211 and DA9212

Datasheet

Company confidential

Data sheet

Version <3.0>

<07-Jan-2015>

CFR0011-120-00 Rev 3

36 of 74

push-pull or open drain (selected via IRQ_TYPE). If an active high IRQ signal is required, it can be

achieved by asserting control IRQ_LEVEL (recommended for push-pull mode).

Examples of this type of information can be critical temperature and voltage, fault conditions, status

changes at GPI ports, and so forth. The event registers hold information about the events that have

occurred. Events are triggered by a status change at the monitored signals. When an event bit is set,

the nIRQ signal is asserted unless this interrupt is masked by a bit in the IRQ mask register. The

nIRQ will not be released until all event registers with asserted bits have been read and cleared. New

events that occur during reading an event register are held until the event register has been cleared,

ensuring that the host processor does not miss them.

GPIO Extender

13.2.4

DA9211 and DA9212 includes a GPIO extender that offers up to five 5 V-tolerant general purpose

input/output ports. Each port is ontrolled via registers from the host processor.

The GPIO3 and GPI4 ports are pin-shared with the 4-WIRE Control Interface. For instance, if

GPIO3_PIN = 01, GPI4_PIN = 01 (Interface selected), the GPIO3 and GPI4 ports will be exclusively

dedicated to output and chip-select signaling for 4-WIRE purposes. If the alternative function is

selected, all GPIOs configuration as per registers 0x58 to 0x5A and 0x145 will be ignored.

GPIs are supplied from the internal rail VDDCORE or VDDIO (selected via GPI_V) and can be

configured to be active high or active low (selected via GPIOx_TYPE). The input signals can be

debounced or directly change the state of the assigned status register GPIx to high or low, according

to the setting of GPIOx_MODE. The debouncing time is configurable via control DEBOUNCE (10 ms

default).

When ever the status has changed to its configured active state (edge sensitive), the assigned event

Whenever DA9211 and DA9212 is enabled and enters ON mode (also when enabled changing the

setting of GPIOx_PIN) the GPI status bits are initiated towards their configured passive state. This

ensures that already active signals are detected, and that they create an event immediately after the

GPI comparators are enabled.

The buck enable signal (BUCKx_EN) can be controlled directly via a GPI, if so configured in the

BUCKA_GPI and BUCKB_GPI registers. If it is required that GPI ports do not generate an event

when configured for the HW control of the switching regulator, the relative mask bit should be set.

GPIs can alternatively be selected to toggle the VBUCKA_SEL and VBUCKB_SEL from rising and

falling edges at this inputs. Apart from changing the regulator output voltage this also provides

hardware control of the regulator mode (normal/low power mode) from the settings of Error!

eference source not found., Error! Reference source not found., Error! Reference source not

found., and Error! Reference source not found. (enabled if BUCKA_MODE or BUCKB_MODE =

‘00’).

All GPI ports have the additional option of activating a 100 kΩ pull-down resistor via GPIOx_PUPD,

which ensures a well defined level in case the input is not actively driven.

If enabled via ADDR_SEL_CONF, the I2C address selection can be assigned to a specific GPI. An

active voltage level at the selected GPI configures the slave address of DA9211 and DA9212 to

IF_BASE_ADDR1 while a passive voltage level configures the slave address to IF_BASE_ADDR2. If

no GPI is selected then the IF_BASE_ADDR1 is automatically used.

If defined as an output, GPIOs can be configured to be open-drain or push-pull. If configured as

push-pull, the supply rail is VDDIO. By disabling the internal 120

kΩ pull-up resistor in open-drain

mode, the GPO can also be supplied from an external rail. The output state will be assigned as

configured by the GPIO register bit GPIOx_MODE.

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