STA7360 datasheet(12/18 Pages) STMICROELECTRONICS

12 / 18 page

STA7360

12/18

Figure 25. ICV - PNP Gain vs. IC

Figure 26. ICV - PNP VCE(sat) vs. IC

Figure 27. ICV - PNP cut-off frequency vs. IC

OUTPUT STAGE

Poor current capability and low cutoff frequency are

well known limits of the standard lateral PNP. Com-

posite PNP-NPN power output stages have been

widely used, regardless their high saturation drop.

This drop can be overcome only at the expense of ex-

ternal components, namely, the bootstrap capacitors.

The availability of 4A isolated collector PNP (ICV

PNP) adds versatility to the design. The performance

of this component, in terms of gain, VCEsat and cut-

off frequency, is shown in fig. 25, 26, 27 respectively.

It is realized in a new bipolar technology, character-

ized by top-bottom isolation techniques, allowing the

implementation of low leakage diodes, too. It guaran-

tees BVCEO >20V and BVCBO >50V both for NPN

and PNP transistors. Basically, the connection

shown in fig. 13 has been chosen. First of all because

its voltage swing is rail-to-rail, limited only by the VC-

Esat of the output transistors, which are in the range

of 0.3W each. Then, the gain VOUT/VIN is greater

than unity, approximately 1+R2/R1. (VCC/2 is fixed

by an auxiliary amplifier common to both channel). It

is possible, controlling the amount of this local feed-

back, to force the loop gain (A * b) to less than unity

at frequencies for which the phase shift is 180°. This

means that the output buffer is intrinsically stable and

not prone to oscillation.

Figure 28. The New Output Stage

In contrast, with the circuit of fig. 29, the solution

adopted to reduce the gain at high frequencies is the

use of an external RC network.

AMPLIFIER BLOCK DIAGRAM

The block diagram of each voltage amplifier is shown

in fig. 30. Regardless of production spread, the cur-

rent in each final stage is kept low, with enough mar-

gin on the minimum, below which cross-over

distortion would appear.

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