SN74LVC74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

SCAS287B – JANUARY 1993 – REVISED JULY 1995

1

POST OFFICE BOX 655303

CMOS) Submicron Process

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

(C = 200 pF, R = 0)

Per JEDEC Standard JESD-17

Small-Outline (D), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages

description

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,

data at the D input may be changed without affecting the levels at the outputs.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

The SN74LVC74 is characterized for operation from – 40

°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK

D

Q

Q

L

H

X

X

H

L

H

LX

XL

H

L

LX

X

H†

H†

H

H

↑

HH

L

H

H

↑

LL

H

H

H

L

X

Q0

Q0

† This configuration is nonstable; that is, it does not

persist when PRE or CLR returns to its inactive

(high) level.

Copyright

© 1995, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D, DB, OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1CLR

1D

1CLK

1PRE

1Q

1Q

GND

2CLR

2D

2CLK

2PRE

2Q

2Q