SN74LVC74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

SCAS287B – JANUARY 1993 – REVISED JULY 1995

4

POST OFFICE BOX 655303

(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

(INPUT)

(OUTPUT)

MIN

MAX

MIN

MAX

fmax

100

83

MHz

tpd

CLK

QorQ

1

6.5

7

ns

tpd

PRE or CLR

Q or Q

1

8

9

ns

tsk(o)†

1

ns

† Skew between any two outputs of the same package switching in the same direction. This parameter is warranted but not production tested.

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance per flip-flop

CL = 50 pF,

f = 10 MHz

27

pF