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GXM датащи(PDF) 234 Page - National Semiconductor (TI) |
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GXM датащи(HTML) 234 Page - National Semiconductor (TI) |
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234 / 244 page ![]() www.national.com 234 Revision 3.1 Instruction Set (Continued) 9.6 NATIONAL SEMICONDUCTOR EXTENDED MMX INSTRUCTION SET National Semiconductor has added instructions to its implementation of the MMX Architecture in order to facili- tate writing of multimedia applications. In general, these instructions allow more efficient implementation of multi- media algorithms, or more precision in computation than can be achieved using the basic set of MMX instructions. All of the added instructions follow the SIMD (single instruction, multiple data) format. Many of the instructions add flexibility to the MMX architecture by allowing both source operands of an instruction to be preserved, while the result goes to a separate register that is derived from the input. Table 9-33 on page 235 summarizes the Extended MMX Instructions. The abbreviations used in the table are listed in Table 9-32. Configuration control register CCR7(0) at location EBh must be set to allow the execution of the Extended MMX instructions. Table 9-32. Extend MMX Instruction Set Table Legend Abbreviation Description <---- Result written [11 mm reg] Binary or binary groups of digits mm One of eight 64-bit MMX registers reg A general purpose register <--sat-- If required, the resultant data is saturated to remain in the associated data range <--move-- Source data is moved to result location [byte] Eight 8-bit bytes are processed in parallel [word] Four 16-bit WORD are processed in paral- lel [dword] Two 32-bit DWORDs are processed in par- allel [qword] One 64-bit QWORD is processed [sign xxx] The BYTE, WORD, DWORD or QWORD most significant bit is a sign bit mm1, mm2 MMX Register 1, MMX Register 2 mod r/m Mod and r/m byte encoding (page 6-6 of this manual) pack Source data is truncated or saturated to next smaller data size, then concatenated. packdw Pack two DWORDs from source and two DWORDs from destination into four WORDs in destination register. packwb Pack four WORDs from source and four WORDs from destination into eight BYTEs in destination register. |
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