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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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GXM датащи(PDF) 231 Page - National Semiconductor (TI) |
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GXM датащи(HTML) 231 Page - National Semiconductor (TI) |
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231 / 244 page  Revision 3.1 231 www.national.com Instruction Set (Continued) PCMPEQD Packed Dword Compare for Equality MMX Register 2 with MMX Register 1 0F76 [11 mm1 mm2] MMX reg 1 [dword] <--FFFF FFFFh-- if MMX reg 1 [dword] = MMX reg 2 [dword] MMX reg 1 [dword]<--0000 0000h--if MMX reg 1[dword] NOT = MMX reg 2 [dword] 1/1 Memory with MMX Register 0F76 [mod mm r/m] MMX reg [dword] <--FFFF FFFFh-- if memory[dword] = MMX reg [dword] MMX reg [dword] <--0000 0000h-- if memory[dword] NOT = MMX reg [dword] 1/1 PCMPEQW Packed Word Compare for Equality MMX Register 2 with MMX Register 1 0F75 [11 mm1 mm2] MMX reg 1 [word] <--FFFFh-- if MMX reg 1 [word] = MMX reg 2 [word] MMX reg 1 [word]<--0000h-- if MMX reg 1 [word] NOT = MMX reg 2 [word] 1/1 Memory with MMX Register 0F75 [mod mm r/m] MMX reg [word] <--FFFFh-- if memory[word] = MMX reg [word] MMX reg [word] <--0000h-- if memory[word] NOT = MMX reg [word] 1/1 PCMPGTB Pack Compare Greater Than Byte MMX Register 2 to MMX Register 1 0F64 [11 mm1 mm2] MMX reg 1 [byte] <--FFh-- if MMX reg 1 [byte] > MMX reg 2 [byte] MMX reg 1 [byte]<--00h-- if MMX reg 1 [byte] NOT > MMX reg 2 [byte] 1/1 Memory with MMX Register 0F64 [mod mm r/m] MMX reg [byte] <--FFh-- if memory[byte] > MMX reg [byte] MMX reg [byte] <--00h-- if memory[byte] NOT > MMX reg [byte] 1/1 PCMPGTD Pack Compare Greater Than Dword MMX Register 2 to MMX Register 1 0F66 [11 mm1 mm2] MMX reg 1 [dword] <--FFFF FFFFh-- if MMX reg 1 [dword] > MMX reg 2 [dword] MMX reg 1 [dword]<--0000 0000h--if MMX reg 1 [dword]NOT > MMX reg 2 [dword] 1/1 Memory with MMX Register 0F66 [mod mm r/m] MMX reg [dword] <--FFFF FFFFh-- if memory[dword] > MMX reg [dword] MMX reg [dword] <--0000 0000h-- if memory[dword] NOT > MMX reg [dword] 1/1 PCMPGTW Pack Compare Greater Than Word MMX Register 2 to MMX Register 1 0F65 [11 mm1 mm2] MMX reg 1 [word] <--FFFFh-- if MMX reg 1 [word] > MMX reg 2 [word] MMX reg 1 [word]<--0000h-- if MMX reg 1 [word] NOT > MMX reg 2 [word] 1/1 Memory with MMX Register 0F65 [mod mm r/m] MMX reg [word] <--FFFFh-- if memory[word] > MMX reg [word] MMX reg [word] <--0000h-- if memory[word] NOT > MMX reg [word] 1/1 PMADDWD Packed Multiply and Add MMX Register 2 to MMX Register 1 0FF5 [11 mm1 mm2] MMX reg 1 [dword] <--add-- [dword]<---- MMX reg 1 [sign word]*MMX reg 2[sign word] 2/1 Memory to MMX Register 0FF5 [mod mm r/m] MMX reg 1 [dword] <--add-- [dword] <---- memory [sign word] * Memory [sign word] 2/1 PMULHW Packed Multiply High MMX Register 2 to MMX Register 1 0FE5 [11 mm1 mm2] MMX reg 1 [word] <--upper bits-- MMX reg 1 [sign word] * MMX reg 2 [sign word] 2/1 Memory to MMX Register 0FE5 [mod mm r/m] MMX reg 1 [word] <--upper bits-- memory [sign word] * Memory [sign word] 2/1 PMULLW Packed Multiply Low MMX Register 2 to MMX Register 1 0FD5 [11 mm1 mm2] MMX reg 1 [word] <--lower bits-- MMX reg 1 [sign word] * MMX reg 2 [sign word] 2/1 Memory to MMX Register 0FD5 [mod mm r/m] MMX reg 1 [word] <--lower bits-- memory [sign word] * Memory [sign word] 2/1 POR Bitwise OR MMX Register 2 to MMX Register 1 0FEB [11 mm1 mm2] MMX reg 1 [qword] <--logic OR-- MMX reg 1 [qword], MMX reg 2 [qword] 1/1 Memory to MMX Register 0FEB [mod mm r/m] MMX reg [qword] <--logic OR-- MMX reg [qword], memory[qword] 1/1 PSLLD Packed Shift Left Logical Dword MMX Register 1 by MMX Register 2 0FF2 [11 mm1 mm2] MMX reg 1 [dword] <--shift left, shifting in zeroes by MMX reg 2 [dword]-- 1/1 MMX Register by Memory 0FF2 [mod mm r/m] MMX reg [dword] <--shift left, shifting in zeroes by memory[dword]-- 1/1 MMX Register by Immediate 0F72 [11 110 mm] # MMX reg [dword] <--shift left, shifting in zeroes by [im byte]-- 1/1 PSLLQ Packed Shift Left Logical Qword MMX Register 1 by MMX Register 2 0FF3 [11 mm1 mm2] MMX reg 1 [qword] <--shift left, shifting in zeroes by MMX reg 2 [qword]-- 1/1 MMX Register by Memory 0FF3 [mod mm r/m] MMX reg [qword] <--shift left, shifting in zeroes by [qword]-- 1/1 MMX Register by Immediate 0F73 [11 110 mm] # MMX reg [qword] <--shift left, shifting in zeroes by [im byte]-- 1/1 PSLLW Packed Shift Left Logical Word MMX Register 1 by MMX Register 2 0FF1 [11 mm1 mm2] MMX reg 1 [word] <--shift left, shifting in zeroes by MMX reg 2 [word]-- 1/1 MMX Register by Memory 0FF1 [mod mm r/m] MMX reg [word] <--shift left, shifting in zeroes by memory[word]-- 1/1 MMX Register by Immediate 0F71 [11 110mm] # MMX reg [word] <--shift left, shifting in zeroes by [im byte]-- 1/1 Table 9-31. MMX Instruction Set Summary (Continued) MMX Instructions Opcode Operation and Clock Count (Latency/Throughput) |
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