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QL8050 датащи(PDF) 26 Page - List of Unclassifed Manufacturers

номер детали QL8050
подробное описание детали  LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
PDF  49 Pages
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производитель  ETC [List of Unclassifed Manufacturers]
домашняя страница  
Logo ETC - List of Unclassifed Manufacturers

QL8050 датащи(HTML) 26 Page - List of Unclassifed Manufacturers

Back Button QL8050 Datasheet HTML 22Page - List of Unclassifed Manufacturers QL8050 Datasheet HTML 23Page - List of Unclassifed Manufacturers QL8050 Datasheet HTML 24Page - List of Unclassifed Manufacturers QL8050 Datasheet HTML 25Page - List of Unclassifed Manufacturers QL8050 Datasheet HTML 26Page - List of Unclassifed Manufacturers QL8050 Datasheet HTML 27Page - List of Unclassifed Manufacturers QL8050 Datasheet HTML 28Page - List of Unclassifed Manufacturers QL8050 Datasheet HTML 29Page - List of Unclassifed Manufacturers QL8050 Datasheet HTML 30Page - List of Unclassifed Manufacturers Next Button
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tSWA
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the
active edge of the WRITE CLOCK
0.675 ns
-
tHWA
WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active
edge of the WRITE CLOCK
0 ns
-
tSWD
WD setup time to WCLK: time the WRITE DATA must be stable before the active
edge of the WRITE CLOCK
0.654 ns
-
tHWD
WD hold time to WCLK: time the WRITE DATA must be stable after the active edge
of the WRITE CLOCK
0 ns
-
tSWE
WE setup time to WCLK: time the WRITE ENABLE must be stable before the active
edge of the WRITE CLOCK
0.623 ns
-
tHWE
WE hold time to WCLK: time the WRITE ENABLE must be stable after the active
edge of the WRITE CLOCK
0 ns
-
tWCRD
WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the
time when the data is available at RD
-
4.38 ns
tSWA
tSWD
tSWE
tHWA
tHWD
tHWE
tWCRD
old data
new data
WCLK
WA
WD
WE
RD



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