HT24LC08

Rev. 1.30

5

November 25, 2003

The HT24LC08 supports three read operations,

namely, current address read, random address read

and sequential read. During read operation execution,

the read/write select bit should be set to

²1².

The internal data word address counter maintains the

last address accessed during the last read or write op-

eration, incremented by one. This address stays valid

between operations as long as the chip power is main-

tained. The address roll over during read from the last

byte of the last memory page to the first byte of the first

page. The address roll over during write from the last

byte of the current page to the first byte of the same

page. Once the device address with the read/write se-

lect bit set to one is clocked in and acknowledged by

the EEPROM, the current address data word is seri-

ally clocked out. The microcontroller should respond

with a

²no ACK² signal (high) followed by a stop condi-

tion (refer to Current read timing).

A random read requires a dummy byte write sequence

to load in the data word address which is then clocked

in and acknowledged by the EEPROM. The

microcontroller must then generate another start con-

dition. The microcontroller now initiates a current ad-

dress read by sending a device address with the

read/write select bit high. The EEPROM acknowl-

edges the device address and serially clocks out the

data word. The microcontroller should respond with a

²no ACK² signal (high) followed by a stop condition

(refer to Random read timing).

Sequential reads are initiated by either a current ad-

dress read or a random address read. After the

microcontroller receives a data word, it responds with

an acknowledgment. As long as the EEPROM re-

ceives an acknowledgment, it will continue to incre-

ment the data word address and serially clock out

sequential data words. When the memory address

limit is reached, the data word address will roll over

and the sequential read continues. The sequential

read operation is terminated when the microcontroller

responds with a

²no ACK² signal (high) followed by a

stop condition.

P

D e v i c e a d d r e s s

W o r d a d d r e s s

A C K

S t o p

S t a r t

S D A

A C K

N o A C K

S

A C K

D A T A

S

A 2 A 1 A 0

D e v i c e a d d r e s s

S t a r t

Random Read Timing

A 2 A 1 A 0

S

P

D e v i c e a d d r e s s

D A T A

A C K

S t o p

S t a r t

S D A

N o A C K

Current Read Timing

P

D e v i c e a d d r e s s

D A T A n

S t o p

S t a r t

S D A

A C K

S

A C K

D A T A n + 1

D A T A n + x

N o A C K

Sequential Read Timing