Symbol

Parameter

Remark

Standard Mode*

±10%

Unit

Min.

Max.

Min.

Max.

Output Valid from Clock

¾¾

3500

¾

900

ns

Bus Free Time

Time in which the bus

must be free before a new

transmission can start

4700

¾

1200

¾

ns

Input Filter Time Constant

(SDA and SCL Pins)

Noise suppression time

¾

100

¾

50

ns

Write Cycle Time

¾¾

5

¾

5ms

Notes: These parameters are periodically sampled but not 100% tested

For relative timing, refer to timing diagrams

HT24LC08

Rev. 1.30

3

November 25, 2003

Functional Description

The SCL input is used for positive edge clock data into

each EEPROM device and negative edge clock data

out of each device.

The SDA pin is bidirectional for serial data transfer.

The pin is open drain driven and may be wired-OR

with any number of other open drain or open collector

devices.

The HT24LC08 uses the A2 input for hard wire ad-

dressing and a total of two 8K devices may be ad-

dressed on a single bus system. The A0 and A1 pins

have no connection.

The HT24LC08 has a write protect pin that provides

hardware data protection. The write protect pin allows

normal read/write operations when the connection is

grounded. When the write protect pin is connected to

ates as shown in the following table.

WP Pin Status

Protect Array

Full Array (8K)

Normal Read/Write Operations

Memory Organization

Internally organized with 1024 8-bit words, the 8K re-

quires a 10-bit data word address for random word ad-

dressing.

Device Operations

Data transfer may be initiated only when the bus is not

busy. During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

data line while the clock line is high will be interpreted

as a START or STOP condition.

A high-to-low transition of SDA with SCL high is a start

condition which must precede any other command

(refer to Start and Stop Definition Timing diagram).

A low-to-high transition of SDA with SCL high is a stop

condition. After a read sequence, the stop command

will place the EEPROM in a standby power mode (re-

fer to Start and Stop Definition Timing Diagram).

All addresses and data words are serially transmitted

to and from the EEPROM in 8-bit words. The

EEPROM sends a zero to acknowledge that it has re-

ceived each word. This happens during the ninth clock

cycle.

Device Addressing

The 8K EEPROM device requires an 8-bit device ad-

dress word following a start condition to enable the chip

for a read or write operation. The device address word

consist of a mandatory one, zero sequence for the first

four most significant bits (refer to the diagram showing

the Device Address). This is common to all the

EEPROM device.

The 8K EEPROM uses the A2 device address bit with

the next two bits for memory page addressing. The A2

bit must compare its corresponding hard-wired input

pin. The A1 and A0 pins have no connection.

S C L

S D A

D a t a a l l o w e d

t o c h a n g e

A d d r e s s o r

a c k n o w l e d g e

v a l i d

S t o p

c o n d i t i o n

S t a r t

c o n d i t i o n

N o A C K

s t a t e