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CS5394 датащи(PDF) 16 Page - Cirrus Logic

номер детали CS5394
подробное описание детали  117 DB 48KHZ AUDIO A/D CONVERTER
PDF  22 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5394 датащи(HTML) 16 Page - Cirrus Logic

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CS5394
16
DS258PP4
MCLKD - Digital Section Input Clock, Pin 20.
MCLKD clocks the digital filter and must be connected to MCLKA. The required MCLKD
frequency is determined by the desired sample rate. A MCLKD of 12.288MHz corresponds to
Fs equal to 48 kHz. MCLKA must be connected to MCLKD.
PDN - Power Down, Pin 19.
When high, the device enters power down. Upon returning low, the device enters normal
operation and issues commands to initialize the voltage reference and synchronize the analog
and digital sections of the device.
S/M - Slave or Master Mode, Pin 17.
When high, the device is configured for Slave mode where LRCK and SCLK are inputs. The
device is configured for Master mode where LRCK and SCLK are outputs when S/M is low.
Digital Outputs
DACTL- Digital to Analog Control Output, Pin 9.
Must be connected to ADCTL. This signal enables communication between the digital and
analog circuits.
SDATA - Digital Audio Data Output, Pin 16.
The 24-bit audio data is presented MSB first, in 2’s complement format. This pin has a internal
pull-down resistor and must remain low during the power-up sequence to avoid accessing a test
mode.
Digital Inputs or Outputs
LRCK - Left/Right Clock, Pin 13.
LRCK determines which channel, left or right, is to be output on SDATA. The relationship
between LRCK, SCLK and SDATA is controlled by the Digital Format Select (DFS) pin.
Although the outputs for each channel are transmitted at different times, Left/Right pairs
represent simultaneously sampled analog inputs. In master mode, LRCK is an output whose
frequency is equal to Fs. In Slave Mode, LRCK is an input whose frequency must be equal to
Fs.
SCLK - Serial Data Clock, Pin 14.
Clocks the individual bits of the serial data from SDATA. The relationship between LRCK,
SCLK and SDATA is controlled by the Digital Format Select (DFS) pin. In master mode,
SCLK is an output clock at 64
× Fs. In slave mode, SCLK is an input which requires a
continuously supplied clock at any frequency from 48
× to 128× Fs (64× is recommended).



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