TSB43AB21 datasheet(39/109 Pages) TI

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3–18

3.24 Link Enhancement Control Register

The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial

EEPROM, if present. After these bits are set to 1, their functionality is enabled only if bit 22 (aPhyEnhanceEnable)

in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is

set to 1. See Table 3–22 for a complete description of the register contents.

Bit

Name

Link enhancement control

Type

Default

Bit

Name

Link enhancement control

Type

R/W

Default

Link enhancement control

Offset:

F4h

Type:

Read/Write, read-only

Default:

0000 1000h

Table 3–22. Link Enhancement Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31–16

RSVD

Reserved. Bits 31–16 return 0s when read.

dis_at_pipeline

R/W

Disable AT pipelining. When bit 15 is set to 1, out-of-order AT pipelining is disabled.

RSVD

Reserved.

13–12

atx_thresh

R/W

This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the

TSB43AB21 device retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward

operation.

00 = Threshold ~ 2K bytes resulting in a store-and-forward operation

01 = Threshold ~ 1.7K bytes (default)

10 = Threshold ~ 1K bytes

11 = Threshold ~ 512 bytes

These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7K-byte

threshold is optimal. Changing this value may increase or decrease the 1394 latency depending on

the average PCI bus latency.

Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds

or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than

the AT threshold, the remaining data must be received before the AT FIFO is emptied; otherwise, an

underrun condition occurs, resulting in a packet error at the receiving node. As a result, the link then

commences store-and-forward operation. Wait until it has the complete packet in the FIFO before

retransmitting it on the second attempt to ensure delivery.

An AT threshold of 2K results in store-and-forward operation, which means that asynchronous data

will not be transmitted until an end-of-packet token is received. Restated, setting the AT threshold to

2K results in only complete packets being transmitted.

Note that this device always uses store-and-forward when the asynchronous transmit retries register

at OHCI offset 08h (see Section 4.3, Asynchronous Transmit Retries Register) is cleared.

RSVD

Reserved. Bit 11 returns 0 when read.

enab_mpeg_ts

R/W

Enable MPEG CIP timestamp enhancement. When bit 9 is set to 1, the enhancement is enabled for

MPEG CIP transmit streams (FMT = 20h).

RSVD

Reserved. Bit 9 returns 0 when read.

enab_dv_ts

R/W

Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV

CIP transmit streams (FMT = 00h).

enab_unfair

R/W

Enable asynchronous priority requests. iOHCI-Lynx

 compatible. Setting bit 7 to 1 enables the link

to respond to requests with priority arbitration. It is recommended that this bit be set to 1.

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