PC87591L datasheet(159/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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Frame Select Register (UFRS)

This byte-wide read/write register controls the selection of the frame format, including number of data bits, number of stop

bits and parity. The register is cleared (0016) on reset.

Location: 00 FD2816

Type: R/W

Bit

76543210

Name

Reserved

PEN

PSEL

XB9

STP

CHAR

Reset

00000000

Bit

Description

1-0

CHAR. Selects the number of data bits per frame. Note that the parity bit is not included in the number of data

bits.

Bits

1 0

Description

0 0:

Frame contains eight data bits

0 1:

Frame contains seven data bits

1 0:

Frame contains nine data bits

1 1:

Loopback mode selected; frame contains nine data bits.

STP. Programs the number of stop bits to be transmitted.

0: One stop bit transmitted

1: Two stop bits transmitted

XB9. Contains the value of the 9th data bit for transmission only. The bit has no effect while operating with seven

or eight data bits per frame.

0: Transmit 0 as 9th data bit

1: Transmit 1 as 9th data bit

5-4

PSEL. Controls the mode of parity bit generation and checking. Note that while operating with nine data bits-

per-frame, the parity bit is omitted. In this case, the value of PSEL has no effect.

Bits

5 4

Description

0 0:

Odd parity

0 1:

Even parity

1 0:

Mark (1)

1 1:

Space (0)

PEN. Enables or disables the generation of a parity bit generation and parity check. Note that there is no parity

bit while operating in the nine data bits-per-frame mode. In this case, this bit has no effect.

0: Parity disabled

1: Parity enabled

Reserved.

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