PC87591L datasheet(155/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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Figure 55. Seven Data Bit Frame Options

The format shown in Figure 56 consists of one start bit, eight data bits (excluding parity) and one or two stop bits. If parity

bit generation is enabled by setting the PEN bit, a parity bit is generated and transmitted following the eight data bits.

Figure 56. Eight Data Bit Frame Options

The format shown in Figure 57 consists of one start bit, nine data bits and one or two stop bits. This format also supports

the USART attention feature. When operating in this format, all eight bits of UTBUF and URBUF are used for data. The ninth

data bit is transmitted and received using two bits in the control registers, called STPXB9 and RB9. Parity is not generated

or verified in this mode.

Figure 57. Nine Data Bit Frame Options

Baud Rate Generator

The Baud Rate Generator provides the basic baud clock from the system clock. The system clock is passed through a two-

stage divider chain consisting of a 5-bit baud rate pre-scaler (PSC) and an 11-bit baud rate divisor (DIV).

The correspondences between the 5-bit pre-scaler select (PSC) and pre-scaler factors are shown in Table 21.

START

BIT

7-BIT DATA

START

BIT

7-BIT DATA

START

BIT

7-BIT DATA

START

BIT

7-BIT DATA

START

BIT

8-BIT DATA

START

BIT

8-BIT DATA

START

BIT

8-BIT DATA

START

BIT

8-BIT DATA

START

BIT

9-BIT DATA

START

BIT

9-BIT DATA

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