PC87591L datasheet(162/437 Pages) NSC

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Embedded Controller Modules (Continued)

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162

Revision 1.07

Interrupt Control Register (UICTRL)

This byte-wide register contains the interrupt enable bits and the interrupt status flags. The register is set to 0116 on reset.

Location: 00 FD2416

Type: Varies per bit

4.9.5

Usage Hints

Calculating the Baud Rate in Asynchronous Mode

The equation for calculating the baud rate is:

BR = SYS_CLK/(16xNxP)

where:

●

BR is the baud rate

●

SYS_CLK is the system clock

●

N is the value of the baud rate divisor + 1

●

P is the pre-scaler divide factor selected by the value in the PSR register

Assuming a system clock of 5 MHz and a desired baud rate of 9600, the NxP term, according to the equation above, is:

NxP = (5x10

6)/(16x9600) = 32.552

The NxP term is then divided by each pre-scaler factor in Table 21 on page 156 to obtain a value closest to an integer. The

factor for this example is 6.5:

N = 32.552/6.5 = 5.008 (N = 5)

Bit

76543210

Name

EEI

ERI

ETI

Reserved

RBF

TBE

Reset

00000001

Bit

Type

Description

0RO

TBE. The bit is set by the hardware when the USART transfers data from UTBUF register to TSFT

on reset.

0: Transmit buffer not empty

1: Transmit buffer empty

1RO

RBF. The bit is set by the hardware when the USART has received a complete data frame and

transferred the data from RSFT register to URBUF register. The bit is automatically cleared when

RBUF register is read.

0: Receive buffer not full. New data has not been transferred to RBUF since the last time it was read.

1: Receive buffer full. RBUF contains new data since the last time it was read.

4-2

Reserved.

R/W

ETI. An interrupt is generated when the TBE ﬂag is set. Read/write bit.

0: Disable transmitter interrupt

1: Enable transmitter interrupt

R/W

ERI. An RX interrupt is generated when the RBF ﬂag is set. Read/write bit.

0: Disable receiver interrupt

1: Enable receiver interrupt

R/W

ETI. An RX interrupt is generated when the ERR ﬂag is set, indicating that a receive error has

occurred.

0: Disable receive error interrupt

1: Enable receive error interrupt

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