PC87591L datasheet(104/437 Pages) NSC

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Embedded Controller Modules (Continued)

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104

Revision 1.07

Edge Interrupt Clear Register 0 (IECLR0)

The IECLR register is used to clear pending, edge-triggered interrupts.

Location: 00 FE1216

Type: WO

Edge Interrupt Clear Register 1 (IECLR1)

The IECLR register is used to clear pending, edge-triggered interrupts.

Location: 00 FE1416

Type: WO

4.3.5

Usage Hints

Initializing

The recommended initialization sequence is:

1. Initialize both the INTBASE register and the interrupt stack pointer of the core.

2. Prepare the interrupt routines of the interrupts used.

3. Clear edge interrupt used.

4. Set relevant bits of the peripherals.

5. Set relevant bits in IENAM register.

6. Set PFAIL register.

7. Enable core interrupt.

Clearing

Clearing an interrupt request before it is serviced may cause a spurious interrupt (i.e., when the core detects an interrupt not

reflected by IVCT). Clear interrupt requests only when interrupts are disabled. Clear IENAM bits and ISTAT bits while the

core interrupts are disabled (i.e., bits I and/or E in PSR register are cleared).

Nesting

The IENAM registers can be used in interrupt handlers to allow interrupt nesting. When the core acknowledges an interrupt, it

disables maskable interrupts by clearing bit I in PSR register and executes the interrupt service routine. This routine can enable

nested interrupts by setting bit I in PSR register and can use the IENAM registers to control which interrupts are allowed.

Bit

9876543210

Name

IEC15-1

Res.

Bit

Description

Reserved.

15-1 IEC15-1 (Edge Interrupt Clear). Each bit clears the corresponding bit in ISTAT0 register. Writing to the bit

positions of level-triggered interrupts has no effect. Read always returns FFFF16. IEC15 to IEC1 correspond to

INT15 to INT1, respectively. Each bit is encoded as follows:

0: No effect

1: Pending edge-triggered interrupt cleared

Bit

9876543210

Name

IEC31-16

Bit

Description

15-0 IEC31-16 (Edge Interrupt Clear). Each bit clears the corresponding bit in ISTAT1 register. Writing to the bit

positions of level-triggered interrupts has no effect. Read always returns FFFF16. IEC31 to IEC16 correspond to

INT31 to INT16, respectively. Each bit is encoded as follows:

0: No effect

1: Pending edge-triggered interrupt cleared

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