PC87591L datasheet(103/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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Interrupt Status Register 1 (ISTAT1)

This register indicates which maskable interrupts are pending regardless of the state of the corresponding IENA bits.

Location: 00 FE0C16

Type: RO

Interrupt Enable and Mask Register 0 (IENAM0)

This register controls the enable/disable of the maskable interrupt sources INT0 to INT15. The register is cleared (000016)

on reset.

Location: 00 FE0E16

Type: R/W

Interrupt Enable and Mask Register 1 (IENAM1)

This register controls the enable/disable of the maskable interrupt sources INT16 to INT31. The register is cleared (000016)

on reset.

Location: 00 FE1016

Type: R/W

Bit

9876543210

Name

IST31-16

Reset

000000000000000

Bit

Description

15-0

IST31-16 (Interrupt Status). Each bit indicates if an interrupt event was sent to the ICU; IST31 to IST16

correspond to INT31 to INT16, respectively. Each bit is encoded as follows:

0: Interrupt input to ICU not pending

1: Interrupt input to ICU pending

Bit

9876543210

Name

IENA15-0

Reset

000000000000000

Bit

Description

15-0 IENA15-0 (Interrupt Enable). Each bit enables or disables the corresponding interrupt request INT0 to INT15;

e.g. IENA15 controls INT15. Since INT0 is not used, IENA0 has no effect on the operation of the ICU.

0: Interrupt disabled

1: Interrupt enabled

Bit

9876543210

Name

IENA31-16

Reset

000000000000000

Bit

Description

15-0 IENA31-16 (Interrupt Enable). Each bit enables or disables the corresponding interrupt request INT16 to

INT31; e.g. IENA16 controls INT16.

0: Interrupt disabled

1: Interrupt enabled

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