PC87591L datasheet(236/437 Pages) NSC

236 / 437 page

Embedded Controller Modules (Continued)

www.national.com

236

Revision 1.07

A battery supply pin (VBAT) provides power to the RTC and low-frequency clock oscillator (LFCO), allowing these parts to

continue functioning even in Power Off mode. Some registers are reserved and events recorded. These registers and events

are maintained by VPP, as noted.

Details of the activity of each battery-operable module are provided in the module’s specification.

4.17.3 Switching Between Power Modes

The switching from one power mode to another is done using the protocols described below.

Figure 77 shows the three power modes of the core domain and the transitions between them.

Wake-Up Event

Some of the power-up switchings are based on receiving a wake-up event. This event has three possible sources:

●

A maskable event (from MIWU)

●

A Non-Maskable Interrupt (NMI)

●

An ISE interrupt (from the Debugger interface)

The wake-up is identified by a high level on the maskable event and/or a low-to-high transition on NMI or ISE interrupts.

Once a wake-up event is detected, it is latched until an interrupt acknowledge bus cycle is detected or a reset is applied.

Decreasing Power Consumption

Entering Idle Mode

Enter Idle mode by setting (1) IDLE bit in PMCSR register and then executing the WAIT instruction. WBPSM must be set

before executing WAIT.The HFCG may be disabled to further reduce the power consumption. This is done by writing 1 to

DHF in PMCSR register before executing WAIT.

Entering Power Off Mode

Switch to Power Off mode by turning off the supply to the VCC pins of the PC87591x Note that VDD must be turned off as well.

The PFAIL input may be used to interrupt the PC87591x so that context saving to a non-volatile memory can be completed

and write operations to the RTC can be stopped before the power to the PC87591x is disconnected.

Increasing Activity

Fast Wake-Up from Idle Mode to Active

A hardware wake-up event causes the core domain to switch directly from Idle mode to Active mode. The following sequence

is performed:

1. HDF in PMCSR register is cleared, thus enabling the high-frequency clock (if it was disabled).

2. After waiting for the high-frequency clock to become active (OHFC in PMCSR register is set), the core domain switches

to Active mode.

When in Active mode, Idle bit in PMCSR register is cleared.

Active

Idle

Power Off

Turn off supply

IDLE =1

and WAIT

Turn on power

apply reset

HW event

supply and

Reset

Figure 77. Power Modes and Transitions

PC87591L датащи(PDF) 236 Page - National Semiconductor (TI)

PC87591L датащи(HTML) 236 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL