PC87591L datasheet(239/437 Pages) NSC

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Embedded Controller Modules (Continued)

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4.18 HIGH-FREQUENCY CLOCK GENERATOR (HFCG)

The HFCG generates the high-frequency clock (OSCCLK) based on the system’s 32.768 KHz clock signal. The HFCG out-

put is derived from OSCCLK and generates the host domain clock and the core domain clock. Clock generation is controlled

by the core domain’s PMC module (see Section 4.17 on page 235) and the host domain’s SuperI/O configuration (see

Section 6 on page 335).

To generate OSCCLK, the HFCG includes a programmable frequency multiplier. The core domain clock is derived from

OSCCLK via a programmable pre-scaler; its frequency is in the range of 4 MHz to 20 MHz. The host domain clock is derived

from OSCCLK via a pre-scaler that divides by 2, generating an output of 48 MHz (see Figure 78).

4.18.1 Features

●

Programmable frequency multiplier for a wide range of output frequencies

●

Core domain clock and host domain clock generation

●

Programmable pre-scaler to derive the core domain clock from OSCCLK

●

Separate enable/disable for core domain clock and host domain clock

●

On VCC power-up:

— 4 MHz default core domain clock frequency is set

— Host domain clock is disabled

●

On WATCHDOG reset and Debugger Interface reset:

— If host domain clock is enabled, the 48 MHz clock monitor is initiated

— If host domain clock is disabled, the 4 MHz default core domain clock frequency is set

4.18.2 Functional Description

Figure 78 shows the HFCG blocks.

The frequency multiplier includes a 5-bit variable (N) and a 14-bit variable (M); these variables define the OSCCLK frequen-

cy. There are two software methods to set the frequency of OSCCLK (by changing N and M); the method used depends on

the HFCG state, as described in Section 4.18.3. The methods are:

Software Method 1. Write new values (HFCGML, HFCGMH and HFCGN registers) to a buffer and enable the programma-

ble frequency setting. Either a normal or fast clock setting may be used. The programmable pre-scaler of the core domain

clock is automatically set to a divide by 1; see “PMC Enabled SuperI/O Disabled State” on page 240.

Frequency

Multiplier

N, M, I

32 KHz

Programmable

Control and Status

Host Domain

Clock

Core Domain

Clock

Enable from PMC

Enable from SuperI/O

Pre-Scaler

Parameter Settings

Current Settings

Hardwired Settings

N, M, I for

= Includes software-accessible registers

OSCCLK

Divide by 2

Host Domain

INT to ICU

Figure 78. HFCG Schematic Diagram

= Software

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