SCANSTA112

7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer

General Description

The SCANSTA112 extends the IEEE Std. 1149.1 test bus

into a multidrop test bus environment. The advantage of a

multidrop approach over a single serial scan chain is im-

proved test throughput and the ability to remove a board

from the system and retain test access to the remaining

modules. Each SCANSTA112 supports up to 7 local

IEEE1149.1 scan chains which can be accessed individually

or combined serially.

Addressing is accomplished by loading the instruction regis-

ter with a value matching that of the Slot inputs. Backplane

and inter-board testing can easily be accomplished by park-

ing the local TAP Controllers in one of the stable TAP Con-

troller states via a Park instruction. The 32-bit TCK counter

enables built in self test operations to be performed on one

port while other scan chains are simultaneously tested.

The STA112 has a unique feature in that the backplane port

and the LSP0 port are bidirectional. They can be configured

to alternatively act as the master or slave port so an alternate

test master can take control of the entire scan chain network

from the LSP0 port while the backplane port becomes a

slave.

Features

n

True IEEE 1149.1 hierarchical and multidrop

addressable capability

n

The 8 address inputs support up to 249 unique slot

addresses, an Interrogation Address, Broadcast

Address, and 4 Multi-cast Group Addresses (address

000000 is reserved)

n

7 IEEE 1149.1-compatible configurable local scan ports

n

Bi-directional Backplane and LSP

interchangeable slave ports

n

Capable of ignoring TRST of the backplane port when it

becomes the slave.

n

Stitcher Mode bypasses level 1 and 2 protocols

n

Mode Register

selected for insertion into the scan chain individually, or

serially in groups of two or three

n

Transparent Mode can be enabled with a single

instruction to conveniently buffer the backplane IEEE

1149.1 pins to those on a single local scan port

n

General purpose local port passthrough bits are useful

for delivering write pulses for Flash programming or

monitoring device status.

n

Known Power-up state

n

TRST on all local scan ports

n

32-bit TCK counter

n

16-bit LFSR Signature Compactor

n

Local TAPs can become TRI-STATE via the OE input to

allow an alternate test master to take control of the local

TAPs (LSP

n

3.0-3.6V V

n

Supports live insertion/withdrawal

20051250

FIGURE 1. Typical use of SCANSTA112 for board-level management of multiple scan chains.

May 2004

© 2004 National Semiconductor Corporation

DS200512

www.national.com