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SCANSTA112 датащи(PDF) 2 Page - National Semiconductor (TI) |
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SCANSTA112 датащи(HTML) 2 Page - National Semiconductor (TI) |
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2 / 15 page ![]() Introduction The SCANSTA112 is the third device in a series that enable multi-drop address and multiplexing of IEEE-1149.1 scan chains. The SCANSTA112 is a superset of its predecessors - the SCANPSC110 and the SCANSTA111. The STA112 has all features and functionality of these two previous devices. The STA112 is essentially a support device for the IEEE 1149.1 standard. It is primarily used to partition scan chains into managable sizes, or to isolate specific devices onto a seperate chain (Figure 1). The benefits of multiple scan chains are improved fault isolation, faster test times, faster programiing times, and smaller vector sets. In addition to scan chain partitioning, the device is also addressable for use in a multidrop backplane environment (Figure 2). In this configuration, multiple IEEE-1149.1 acces- sible cards with an STA112 on board can utilize the same backplane test bus for system-level IEEE-1149.1 access. This approach facilitates a system-wide commitment to structural test and programming throughout the entire sys- tem life sycle. Architecture Figure 3 shows the basic architecture of the ’STA112. The device’s major functional blocks are illustrated here. The TAP Controller, a 16-state state machine, is the central control for the device. The instruction register and various test data registers can be scanned to exercise the various functions of the ’STA112 (these registers behave as defined in IEEE Std. 1149.1). The ’STA112 selection controller provides the functionality that allows the 1149.1 protocol to be used in a multi-drop environment. It primarily compares the address input to the slot identification and enables the ’STA112 for subsequent scan operations. The Local Scan Port Network (LSPN) contains multiplexing logic used to select different port configurations. The LSPN control block contains the Local Scan Port Controllers (LSPC) for each Local Scan Port (LSP 0, LSP1 ... LSPn). This control block receives input from the ’STA112 instruction register, mode registers, and the TAP controller. Each local port contains all four boundary scan signals needed to inter- face with the local TAPs plus the optional Test Reset signal (TRST). The TDI/TDO Crossover Master/Slave logic is used to define the bidirectional B0 and B1 ports in a Master/Slave configuration. 20051251 FIGURE 2. Example of SCANSTA112 in a multidrop addressable backplane. www.national.com 2 |
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