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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS570LS3135 датащи(PDF) 73 Page - Texas Instruments |
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TMS570LS3135 датащи(HTML) 73 Page - Texas Instruments |
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73 / 170 page  TMS570LS3135, TMS570LS2135, TMS570LS2125 www.ti.com SPNS164C – APRIL 2012 – REVISED APRIL 2015 Table 6-20. Device Memory Map (continued) FRAME ADDRESS RANGE RESPONSE FOR ACCESS TO FRAME CHIP FRAME ACTUAL MODULE NAME UNIMPLEMENTED LOCATIONS IN SELECT SIZE SIZE START END FRAME MIBSPI1 RAM PCS[7] 0xFF0E0000 0xFF0FFFFF 128KB 2KB Abort for accesses above 2KB Wrap around for accesses to unimplemented address offsets lower than DCAN3 RAM PCS[13] 0xFF1A0000 0xFF1BFFFF 128KB 2KB 0x7FF. Abort generated for accesses beyond offset 0x800. Wrap around for accesses to unimplemented address offsets lower than DCAN2 RAM PCS[14] 0xFF1C0000 0xFF1DFFFF 128KB 2KB 0x7FF. Abort generated for accesses beyond offset 0x800. Wrap around for accesses to unimplemented address offsets lower than DCAN1 RAM PCS[15] 0xFF1E0000 0xFF1FFFFF 128KB 2KB 0x7FF. Abort generated for accesses beyond offset 0x800. Wrap around for accesses to unimplemented address offsets lower than MIBADC2 RAM PCS[29] 0xFF3A0000 0xFF3BFFFF 128KB 8KB 0x1FFF. Abort generated for accesses beyond 0x1FFF. Wrap around for accesses to unimplemented address offsets lower than MIBADC1 RAM PCS[31] 0xFF3E0000 0xFF3FFFFF 128KB 8KB 0x1FFF. Abort generated for accesses beyond 0x1FFF. Wrap around for accesses to unimplemented address offsets lower than N2HET2 RAM PCS[34] 0xFF440000 0xFF45FFFF 128KB 16KB 0x3FFF. Abort generated for accesses beyond 0x3FFF. Wrap around for accesses to unimplemented address offsets lower than N2HET1 RAM PCS[35] 0xFF460000 0xFF47FFFF 128KB 16KB 0x3FFF. Abort generated for accesses beyond 0x3FFF. HTU2 RAM PCS[38] 0xFF4C0000 0xFF4DFFFF 128KB 1KB Abort HTU1 RAM PCS[39] 0xFF4E0000 0xFF4FFFFF 128KB 1KB Abort FTU RAM PCS[40] 0xFF500000 0xFF51FFFF 128KB 1KB Abort DEBUG COMPONENTS CoreSight Debug CSCS0 0xFFA00000 0xFFA00FFF 4KB 4KB Reads: 0, writes: no effect ROM Cortex-R4F Debug CSCS1 0xFFA01000 0xFFA01FFF 4KB 4KB Reads: 0, writes: no effect ETM-R4 CSCS2 0xFFA02000 0xFFA02FFF 4KB 4KB Reads: 0, writes: no effect CoreSight TPIU CSCS3 0xFFA03000 0xFFA03FFF 4KB 4KB Reads: 0, writes: no effect POM CSCS4 0xFFA04000 0xFFA04FFF 4KB 4KB Abort PERIPHERAL CONTROL REGISTERS FTU PS[23] 0xFFF7A000 0xFFF7A1FF 512B 512B Reads: 0, writes: no effect HTU1 PS[22] 0xFFF7A400 0xFFF7A4FF 256B 256B Reads: 0, writes: no effect HTU2 PS[22] 0xFFF7A500 0xFFF7A5FF 256B 256B Reads: 0, writes: no effect N2HET1 PS[17] 0xFFF7B800 0xFFF7B8FF 256B 256B Reads: 0, writes: no effect N2HET2 PS[17] 0xFFF7B900 0xFFF7B9FF 256B 256B Reads: 0, writes: no effect GPIO PS[16] 0xFFF7BC00 0xFFF7BCFF 256B 256B Reads: 0, writes: no effect MIBADC1 PS[15] 0xFFF7C000 0xFFF7C1FF 512B 512B Reads: 0, writes: no effect MIBADC2 PS[15] 0xFFF7C200 0xFFF7C3FF 512B 512B Reads: 0, writes: no effect FlexRay PS[12]+PS[13] 0xFFF7C800 0xFFF7CFFF 2KB 2KB Reads: 0, writes: no effect I2C PS[10] 0xFFF7D400 0xFFF7D4FF 256B 256B Reads: 0, writes: no effect DCAN1 PS[8] 0xFFF7DC00 0xFFF7DDFF 512B 512B Reads: 0, writes: no effect DCAN2 PS[8] 0xFFF7DE00 0xFFF7DFFF 512B 512B Reads: 0, writes: no effect DCAN3 PS[7] 0xFFF7E000 0xFFF7E1FF 512B 512B Reads: 0, writes: no effect LIN PS[6] 0xFFF7E400 0xFFF7E4FF 256B 256B Reads: 0, writes: no effect SCI PS[6] 0xFFF7E500 0xFFF7E5FF 256B 256B Reads: 0, writes: no effect MibSPI1 PS[2] 0xFFF7F400 0xFFF7F5FF 512B 512B Reads: 0, writes: no effect SPI2 PS[2] 0xFFF7F600 0xFFF7F7FF 512B 512B Reads: 0, writes: no effect Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications 73 Submit Documentation Feedback |
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