TMS570LS3135 datasheet(7/170 Pages) TI1

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TMS570LS3135, TMS570LS2135, TMS570LS2125

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SPNS164C – APRIL 2012 – REVISED APRIL 2015

Revision History

This data manual revision history highlights the technical changes made to the SPNS164B device-specific

data manual to make it an SPNS164C revision.

Scope: Applicable updates to the Hercules™ TMS570 MCU device family, specifically relating to the

TMS570LS31x5/21x5 devices, which are now in the production data (PD) stage of development have

been incorporated.

Changes from August 1, 2013 to April 30, 2015 (from B Revision (July 2013) to C Revision)

Page

•

Section 1 (Device Overview): Updated/Changed section title

................................................................. 1

•

Updated/Changed the N2HET feature

............................................................................................. 1

•

(Device Information): Added table

.................................................................................................. 4

•

Added Section 3, Device Comparison

............................................................................................. 9

•

Section 4 (Terminal Configuration and Functions): Updated/Changed section title

........................................ 10

•

Table 4-2 (PGE Enhanced High-End Timer Modules (N2HET1, N2HET2)): Updated/Changed N2HET1 time

input capture or output compare pin description

................................................................................ 14

•

Table 4-2: Added N2HET1_PIN_nDIS signal DESCRIPTION

................................................................ 14

•

Table 4-2: Updated/Changed N2HET2 time input capture or output compare pin description

........................... 15

•

Table 4-2: Added N2HET2_PIN_nDIS signal DESCRIPTION

................................................................ 15

•

Table 4-3 Updated description about using GIOB[2] on pin 55

.............................................................. 15

•

Table 4-13 (PGE Test and Debug Modules Interface): Updated/Changed TEST pin description

........................ 18

•

Table 4-19 (ZWT Enhanced High-End Timer (N2HET) Modules): Updated/Changed N2HET1 time input capture

or output compare pin description

................................................................................................ 22

•

Table 4-19 Added alternate terminals for N2HET1 pins 17, 19, 21, 23, 25, 27, 29 and 31

............................... 22

•

Table 4-19: Added N2HET1_PIN_nDIS signal DESCRIPTION

............................................................... 22

•

Table 4-19: Updated/Changed N2HET2 time input capture or output compare pin description

.......................... 23

•

Table 4-19: Added N2HET2_PIN_nDIS signal DESCRIPTION

............................................................... 23

•

Table 4-20 Updated description about using GIOB[2] on ball V10

........................................................... 24

•

Table 4-28 (External Memory Interface (EMIF)): Global: Deleted EMIF_RNW pin function.

.............................. 28

•

Table 4-34 (ZWT Test and Debug Modules Interface): Updated/Changed TEST pin description

....................... 34

•

Table 4-36 (No Connects): Deleted NC pins A8, B8, and B9; supported on FlexRay Interface Controller

............. 35

•

Section 5 (Specifications): Updated/Changed section title

.................................................................... 39

•

Section 5.1 (Absolute Maximum Ratings): Reformatted table

................................................................. 39

•

Section 5.1 (Absolute Maximum Ratings): Updated/Changed VCCAD supply voltage range MAX value from "5.5"

to "6.25" V

............................................................................................................................ 39

•

Section 5.1: Updated/Changed ADC input pins input voltage range MAX value from "5.5" to "6.25" V

................. 39

•

Section 5.2 (ESD Ratings): Added table (new)

.................................................................................. 39

•

Section 5.3 (Power-On Hours (POH)): Added table (new)

.................................................................... 39

•

Section 5.8 (Input/Output Electrical Characteristics): Updated/Changed Input Clamp Current from IIC to IIK........... 43

•

Section 5.9 (Thermal Resistance Characteristics): Moved section and updated/changed subsection title.

............ 44

•

Table 5-2 (Thermal Resistance Characteristics (PGE Package)): Added test conditions and added

ΨJT row for

PGE package

........................................................................................................................ 44

•

Table 5-3 (Thermal Resistance Characteristics (ZWT Package)): Added test conditions and added

ΨJT row for

ZWT package

........................................................................................................................ 44

•

Clarified impact of SPI2PC9 register on drive strength of SPI2SOMI pin

.................................................. 45

•

Updated/Changed the MIN value of tv(RST) to 2256tc(OSC) ns .................................................................. 54

•

Section 6.6.1 (Clock Sources): Added Table 6-8, Available Clock Source cross-references

............................. 58

•

Section 6.6.1.1 (Main Oscillator): Added Figure 6-4, Recommended Crystal/Clock Connection cross-reference

..... 58

•

Table 6-10 Added limits for HF LPO after software trim

...................................................................... 60

•

Table 6-13 (Clock Domain Descriptions): Added missing "1" to the VCLKACON clock source selection register

name for VCLKA3 row

.............................................................................................................. 63

•

Section 6.9.1 Added addititional device-specific memory map

................................................................ 70

•

Table 6-20 Corrected size of bank 7 OTP and bank 7 OTP ECC

............................................................ 72

•

Figure 6-12 (TCRAM Block Diagram): Updated/Changed figure, deleted A TCM

.......................................... 80

•

Table 6-25 Added table footnotes identifying the address ranges of the ESRAM PBIST groups

........................ 82

•

Table 6-25 Added RAM power domain information in the table notes

....................................................... 82

•

Table 6-26(Memory Initialization): Updated/Changed N2HET2 RAM ending address from "0xFF57FFFF" to

"0xFF45FFFF"

....................................................................................................................... 83

Revision History

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