TMS570LS3134 datasheet(7/167 Pages) TI1

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TMS570LS3134, TMS570LS2134, TMS570LS2124

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SPNS165B – APRIL 2012 – REVISED MAY 2015

Revision History

This data manual revision history highlights the technical changes made to the SPNS165A device-specific

data manual to make it an SPNS165B revision.

Scope: Applicable updates to the Hercules™ TMS570 MCU device family, specifically relating to the

TMS570LS31x4/21x4 devices, which are now in the production data (PD) stage of development have

been incorporated.

Changes from October 1, 2013 to May 15, 2015 (from A Revision (September 2013) to B Revision)

Page

•

Section 1 (Device Overview): Updated/Changed section title

................................................................. 1

•

Updated/Changed the N2HET feature

............................................................................................. 1

•

Section 1.3(Description): Corrected DMA description, 32 peripheral requests, not 32 control packets

................... 4

•

(Device Information): Added table

.................................................................................................. 4

•

Added Section 3, Device Comparison

............................................................................................. 9

•

Section 4 (Terminal Configuration and Functions): Updated/Changed section title

........................................ 10

•

Table 4-2 (PGE Enhanced Next Generation High-End Timer Modules (N2HET1, N2HET2)): Updated/Changed

N2HET1 time input capture or output compare pin description

............................................................... 14

•

Table 4-2: Added N2HET1_PIN_nDIS signal DESCRIPTION

................................................................ 14

•

Table 4-2: Updated/Changed N2HET2 time input capture or output compare pin description

........................... 15

•

Table 4-2: Added N2HET2_PIN_nDIS signal DESCRIPTION

................................................................ 15

•

Table 4-3: Added table note describing limits on pin 55 when configured as GIOB[2]

................................... 15

•

Table 4-12 (PGE Test and Debug Modules Interface): Updated/Changed TEST pin description

........................ 18

•

Table 4-18 (ZWT Enhanced Next Generation High-End Timer (N2HET) Modules): Updated/Changed N2HET1

time input capture or output compare pin description

.......................................................................... 22

•

Table 4-18: Added alternate terminals for N2HET1 pins 17, 19, 21, 23, 25, 27, 29 and 31

.............................. 22

•

Table 4-18: Added N2HET1_PIN_nDIS signal DESCRIPTION

............................................................... 22

•

Table 4-18: Updated/Changed N2HET2 time input capture or output compare pin description

.......................... 23

•

Table 4-18: Added N2HET2_PIN_nDIS signal DESCRIPTION

............................................................... 23

•

Table 4-19: Updated description about using GIOB[2] on ball V10

.......................................................... 24

•

Table 4-26 (External Memory Interface (EMIF)): Global: Deleted EMIF_RNW pin function.

.............................. 28

•

Table 4-32 (ZWT Test and Debug Modules Interface): Updated/Changed TEST pin description

....................... 34

•

Table 4-34: Changed six BGA balls from NC to Reserved

.................................................................... 34

•

Section 5 (Specifications): Updated/Changed section title

.................................................................... 39

•

Section 5.1 (Absolute Maximum Ratings): Reformatted table

................................................................. 39

•

Section 5.1 (Absolute Maximum Ratings): Updated/Changed VCCAD supply voltage range MAX value from "5.5"

to "6.25" V

............................................................................................................................ 39

•

Section 5.1: Updated/Changed ADC input pins input voltage range MAX value from "5.5" to "6.25" V

................. 39

•

Section 5.2 (ESD Ratings): Added table (new)

.................................................................................. 39

•

Section 5.3 (Power-On Hours (POH)): Added table (new)

.................................................................... 39

•

Table 5-1 (Clock Domain Timing Specifications): Added VCLK, VCLK2, VCLK3, VCLKA1 frequency limits

........... 41

•

Section 5.8 (Input/Output Electrical Characteristics): Updated/Changed Input Clamp Current from IIC to IIK........... 43

•

Section 5.9 (Thermal Resistance Characteristics): Moved section and updated/changed subsection title.

............ 44

•

Table 5-2 (Thermal Resistance Characteristics (PGE Package)): Added test conditions and added

ΨJT row for

PGE package

........................................................................................................................ 44

•

Table 5-3 (Thermal Resistance Characteristics (ZWT Package)): Added test conditions and added

ΨJT row for

ZWT package

........................................................................................................................ 44

•

Clarified impact of SPI2PC9 register on drive strength of SPI2SOMI pin

.................................................. 45

•

Updated/Changed the MIN value of tv(RST) to 2256tc(OSC) ns .................................................................. 54

•

Section 6.5.1: Added Quantity of Breakpoints and Watchpoints

............................................................. 55

•

Section 6.6.1 (Clock Sources): Added Table 6-8, Available Clock Source cross-references

............................. 59

•

Section 6.6.1.1 (Main Oscillator): Added Figure 6-4, Recommended Crystal/Clock Connection cross-reference

..... 59

•

Table 6-13 (Clock Domain Descriptions): Added missing "1" to the VCLKACON clock source selection register

name for VCLKA3 row

.............................................................................................................. 64

•

Section 6.9.1 (Memory Map Diagram): Added additional device-specific memory map

................................... 71

•

Table 6-20 (Device Memory Map): Corrected size of bank 7 OTP and bank 7 OTP ECC

................................ 73

•

Figure 6-12 (TCRAM Block Diagram): Updated/Changed figure, deleted A TCM

.......................................... 81

•

Table 6-25 (PBIST RAM Grouping): Added table footnotes identifying the address ranges of the ESRAM PBIST

groups

................................................................................................................................. 83

Revision History

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