EMC2113 datasheet(54/88 Pages) MICROCHIP

54 / 88 page

RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown

Datasheet

DS20005251A-page 54

 2013 Microchip Technology Inc.

Reading the Interrupt Status Register does not clear the Error Status bit. Reading from any Error Status

Status Registers will have no effect.

7.14.1

Tcrit Status Register

The Tcrit Status Register stores which software enabled temperature channel has caused the

SYS_SHDN pin to be asserted. Each of the temperature channels must be associated with the

SYS_SHDN pin before they can be set (see Section 7.10, "Critical Temperature Limit Registers"). Once

the SYS_SHDN pin is asserted, it will be released when the temperature drops below the threshold

level; however, the individual status bit will not be cleared until read.

Bit 7 - HWS - This bit is set if the hardware set temperature channel caused the SYS_SHDN pin to

be asserted.

7.15

Fan Status Register

The Fan Status Register contains the status bits associated with each fan driver.

Bit 7 - WATCH - This bit is asserted ‘1’ if the Watchdog timer has expired (see Section 6.10, "Watchdog

Timer").

Bit 5 - DRIVE_FAIL - Indicates that the RPM-based Fan Speed Control Algorithm cannot drive the Fan

to the desired target setting at maximum drive. This bit can be masked from asserting the ALERT pin.



‘0’ - The RPM-based Fan Speed Control Algorithm can drive Fan to the desired target setting.



‘1’ - The RPM-based Fan Speed Control Algorithm cannot drive Fan to the desired target setting

at maximum drive.

Bit 1- FAN_SPIN - This bit is asserted ‘1’ if the Spin up Routine for the Fan cannot detect a valid

tachometer reading within its maximum time window. This bit can be masked from asserting the ALERT

pin.

Bit 0 - FAN_STALL - This bit is asserted ‘1’ if the tachometer measurement on the Fan detects a stalled

fan. This bit can be masked from asserting the ALERT pin.

7.16

Interrupt Enable Register

The Interrupt Enable Register controls the masking for each temperature channel. When a channel is

masked, it will not cause the ALERT pin to be asserted when an error condition is detected.

Table 7.22 Fan Status Register

ADDR

R/W

DEFAULT

27h

R-C

Fan Status

WATCH

DRIVE_

FAIL

FAN_

SPIN

FAN_

STALL

00h

Table 7.23 Interrupt Enable Register

ADDR

R/W

DEFAULT

28h

R/W

Interrupt

Enable

PWM_

INT_

---

EXT3_

INT_

EXT2_

INT_

EXT1_

INT_

00h

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