HV583GA-G datasheet(10/22 Pages) MICROCHIP

10 / 22 page

HV583

DS20005461A-page 10

 2015 Microchip Technology Inc.

2.1

High-Voltage Output Pins

(HVOUT0 to HVOUT127)

These

are

the

high-voltage

output

channels

(Push-Pull).

2.2

High-Voltage Power Supply Pins

(VPP)

High-voltage power supply pins for the output channels

(HVOUTn).

2.3

No Connection Pins (NC)

NC pins do not have any functionality on the IC. These

pins should not be connected.

2.4

High-Voltage Ground Pins (PGND)

High-voltage ground pins provide the reference ground

level for the high-voltage output channels.

2.5

Digital Logic Ground Pins (DGND)

Digital Logic Ground pins provide a reference ground

level for the low-voltage section of the IC, shift-regis-

ters, latches and decoders.

2.6

Logic Power Supply Pins (VDD)

Logic power supply pins for the 32-bit shift registers,

128-bit latch and decoders.

2.7

Data Input/Output Pins

(D1A, D2A, D3A, D4A)

Data Input/Output pins are configurable as inputs or

outputs for the shift registers depending on the state of

the Direction pin (DIR).

When DIR is High, pins D1A to D4A are configured as

inputs to the data shift registers. When DIR is Low,

these pins are configured as outputs of the data shift

registers.

2.8

Output Enable Pin (OE)

The Output Enable pin controls the functionality of the

high-voltage output channels.

When OE is High, all HVOUTn channels are enabled

and form a push-pull configuration to operate according

to input data, OL or OH configuration states. When OE

is Low, all HVOUTn channels are forced to a high-

impedance state, regardless of the data stored in the

128-bit latch or the state of the OL and OH pins.

2.9

Latch Enable Pin (LE)

The Latch Enable pin controls the data transfer from

the input shift registers to the 128-bit latch and the

HVOUTn channels.

When LE transitions from Low to High (rising edge),

data is transferred from the 128-bit data latch to the

HVOUTn output channels. When LE is Low, new data

can be clocked into the shift registers.

2.10

Data Input/Output Pins

(D1B, D2B, D3B, D4B)

Data Input/Output pins are configurable as inputs or

outputs for the shift registers, depending on the state of

the Direction pin (DIR).

When DIR is Low, pins D1B to D4B are configured as

inputs to the data shift registers. When DIR is High,

pins are configured as outputs of the data shift

registers.

2.11

Output Low Pin (OL)

The Output Low pin sets all high-voltage output chan-

nels (HVOUT0 to HVOUT127) to a Low-level state

(PGND).

When OL is set Low and OE is High, all the HVOUTn chan-

nels are forced to a Low-level state (PGND), regardless of

the data stored in the 128-bit latch.

2.12

Direction Pin (DIR)

The DIR pin controls the direction of the input data flow

for the input registers, whether it is clockwise (DnB to

DnA) or counter-clockwise (DnA to DnB).

When the DIR pin is set High, data flows from DnA to

DnB. When DIR pin is set Low, data flows from DnB to

DnA. See Table 1-6 for more information.

2.13

Clock Input Pin (CLK)

This is the Clock Input pin for 32-bit input shift registers.

2.14

Output High Pin (OH)

The Output High pin sets all high-voltage output channels

(HVOUT0 to HVOUT127) to a High-level state (VPP).

When OH is Low while OE and OL are High, all the

HVOUTn channels are forced to a High-level state (VPP),

regardless of the data stored in the 128-bit latch. See

Table 1-4 for more information.

2.15

Reset Pin (RST)

The RST pin clears shift registers and the 128-bit latch

data content when it is set High during the rising edge

of the CLK and LE, respectively. See Table 1-5 for

more information.

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