MCP2035 datasheet(41/68 Pages) MICROCHIP

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 2012 Microchip Technology Inc.

DS22304A-page 41

MCP2035

5.21

Low-Current Sleep Mode

The device can stay at an ultra low-current mode

(Sleep mode) when it receives a Sleep command via

the Serial Peripheral Interface (SPI). All circuits includ-

ing the RF Limiter, except the minimum circuitry

required to retain register memory and SPI capability,

will be powered down to minimize the current draw.

Power-on Reset or any SPI command, other than the

Sleep command, is required to wake the device from

Sleep.

5.22

Low-Current Standby Mode

The device is in Standby mode when no input signal is

present on the input pin, but is powered and ready to

receive any incoming signals.

5.23

Low-Current Active Mode

The device is in Low-Current Active mode when an

input signal is present on any input pin and internal

circuitry is switching with the received data.

5.24

Error Detection of Configuration

The Configuration registers are volatile memory.

Therefore, the contents of the registers can be cor-

rupted or cleared by any electrical incidence, such as

battery disconnect. To ensure data integrity, the device

has an error detection mechanism using row and col-

umn parity bits of the Configuration register memory

map. The bit 0 of each register is a row parity bit which

is calculated over the eight Configuration bits (from bit

1 to bit 8). The Column Parity Register (Configuration

lated over the respective columns (Configuration regis-

ters 0 to 5) of the Configuration bits. The STATUS

tion. Parity is to be odd. The parity bit, set or cleared,

makes an odd number of set bits. The user needs to

calculate the row and column parity bits using the

contents of the registers and program them. During

operation, the device continuously calculates the row

and column parity bits of the configuration memory

map. If a parity error occurs, the device lowers the

SCLK/ALERT pin (interrupting the microcontroller

section) indicating the configuration memory has been

corrupted or unloaded and needs to be reprogrammed.

At an initial condition after a Power-on Reset, the

values of the registers are all clear (default condition).

Therefore, the device will issue the parity bit error by

lowering the SCLK/ALERT pin. If the user reprograms

the registers with the correct parity bits, the SCLK/

ALERT pin will be toggled to logic high level

immediately.

The parity bit errors do not change or affect any

functional operation.

Table 5-4 shows an example of the register values and

corresponding parity bits.

TABLE 5-4:

CONFIGURATION REGISTER PARITY BIT EXAMPLE

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(Row Parity)

Configuration Register 0

Configuration Register 1

Configuration Register 2

Configuration Register 3

Configuration Register 4

Configuration Register 5

Configuration Register 6

(Column Parity Register)

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