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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MCP19116 датащи(PDF) 75 Page - Microchip Technology |
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MCP19116 датащи(HTML) 75 Page - Microchip Technology |
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75 / 246 page  2015-2016 Microchip Technology Inc. DS20005479B-page 75 MCP19116/7 FIGURE 10-2: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) 10.4.2 SYNCHRONOUS MASTER RECEIVE MODE Synchronous Master Receive mode works similarly to Asynchronous Receive mode, see Section 10.3.2 “Asynchronous Receive Mode”. In Synchronous Receive mode, reception is enabled by setting either enable bit SREN (RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is sampled on the GPB7/RX/DT/CCD pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, CREN takes precedence. When setting up a Synchronous Master Reception: 1. Initialize the SPBRG register for the appropriate baud rate. 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. CREN and SREN bits are clear. 4. If interrupts are desired, then set enable bit RCIE. 5. If 9-bit reception is desired, then set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF is set when reception is complete and an interrupt is generated if enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. DT pin CK pin Write to TXREG Reg TXIF bit TRMT bit bit0 bit1 bit2 bitn bit7/8 TXEN bit |
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