MCP19116 datasheet(49/246 Pages) MICROCHIP

49 / 246 page

 2015-2016 Microchip Technology Inc.

DS20005479B-page 49

MCP19116/7

6.9

VREF2 Voltage Reference

The VREF2CON register controls a second reference

DAC that can be used externally. For example, it can be

sent off-chip and used to set the current regulation set

point for a MCP1631 Pulse-Width Modulator. The

MCP19116/7 must be configured in Master Mode with

bits MSC<0:1> = 01 in the MODECON register to

connect VREF2 to GPB1. In Stand-Alone mode, VREF2

is not accessible. VREFCON2 holds the digital value

used to set the VREF2 DAC. Since this reference is

intended to go off-chip, there is no pedestal offset

associated with it and it is referenced to GND. It is an

8-bit linear DAC and has a range from 0V to 1.23V (BG)

equating to 255 steps at 9.6 mV/step.

6.10

Analog Peripheral Control

The MCP19116/7 devices have several analog

peripherals, such as the PDRV and SDRV peripherals,

and a weak pull-up on the ISP input.

PDRV and SDRV peripherals are enabled using single

bits, PDRVEN and SDRVEN. The weak pull-up on the

ISP input is enabled using the ISPUEN bit.

These peripherals can be configured to allow

customizable operation. Refer to Register 6-13 for

more information.

6.10.1

MOSFET GATE DRIVER ENABLES

The MCP19116/7 can enable and/or disable the

MOSFET gate driver outputs for the primary drive

(PDRV)

and

the

secondary

drive

(SDRV)

independently. Setting the <PDRVEN> bit in the PE1

<SDRVEN> bit in the PE1 register enables the

secondary drive. Refer to Register 6-13 for details.

6.10.2

MOSFET DRIVER DEAD TIME

The MOSFET drive dead time can be adjusted as

described

Section 6.7

“MOSFET

Driver

Programmable Dead Time”. The dead time can be

set independently for each driver from 16 ns to 256 ns

in increments of 16 ns using the DEADCON register.

Dead time can also be disabled for each driver

independently by setting the bypass bits <PDRVBY>

and <SDRVBY> in the PE1 register.

6.10.3

SECONDARY CURRENT POSITIVE

SENSE PULL-UP

A high-impedance pull-up on the ISP pin can be

configured by setting the <ISPUEN> bit in the PE1

VDD. Refer to Register 6-13 for details.

6.10.4

PWM STEERING

The MCP19116/7 devices have additional control

circuitry to allow open-loop repositioning of the output.

The PWMSTR_PEN bit enables a primary-only PWM

signal of fixed frequency and duty cycle to reposition

the output voltage up. The PWMSTR_SEN bit enables

a secondary-only PWM signal of fixed frequency and

duty cycle to reposition the output voltage down. When

repositioning output voltage down, the output

overvoltage protection must be active along with

PWMSTR_SEN for the PWM to pulse the SDRV.

Frequency and duty cycle are controlled through TMR2

registers PR2 and TMR1L. PWMSTPR_PEN and

PWMSTR_SEN should never be active at the same

time, therefore PWMSTPR_PEN is the dominant bit.

For

quasi-resonant

operation

during

open-loop

repositioning, the DESAT comparator output should be

disabled with the <CDSOE> bit in the DEADCON

VREF2CON: VREF2 VOLTAGE SET POINT REGISTER

R/W-0

VREF27

VREF26

VREF25

VREF24

VREF23

VREF22

VREF21

VREF20

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-0

VREF2<7:0>: Voltage Controlling Current Regulation Set Point bits

VREF2(V) = VBG * N/255 where N is the decimal value written to the VREF2CON Register

<VREF27:VREF20> from 0 to 255

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