PCM3008

SLAS332 – APRIL 2001

10

www.ti.com

PCM audio interface (continued)

0.5 VCC

0.5 VCC

0.5 VCC

0.5 VCC

tLRP

tBCH

tBCL

tBL

tLB

tBCY

tDIS

tDIH

tBDO

tLDO

LRCK

BCK

DIN

DOUT

SYMBOL

DEFINITION

MIN

TYP

MAX

UNITS

tBCY

BCK pulse cycle time

300

ns

tBCH

BCK pulse width high

120

ns

tBCL

BCK pulse width low

120

ns

tBL

BCK rising edge to LRCK edge

40

ns

tLB

LRCK edge to BCK rising edge

40

ns

tLRP

LRCK pulse width

tBCY

tDIS

DIN setup time

40

ns

tDIH

DIN hold time

40

ns

tBDO

DOUT delay time to BCK falling edge

40

ns

tLDO

DOUT delay time to LRCK edge

40

ns

tR

Rising time of all signals

20

ns

tF

Falling time of all signals

20

ns

Figure 5. Audio Data Input/Output Timing

synchronization with digital audio system

PCM3008 operates with LRCK synchronized to the system clock. PCM3008 does not need a specific phase

relationship between LRCK and system clock, but does require the synchronization of LRCK and system clock.

If the relationship between system clock and LRCK changes more than

±4 BCK during one sample period,

changes less than

±4 BCK, re-synchronization does not occur and the above analog/digital output control and

discontinuity do not occur. The following figure illustrates the DAC analog output and ADC digital output for loss

of synchronization. During undefined data periods, some noise may be generated in the audio signal. Also, the

transition of normal to undefined data and undefined data to normal makes a discontinuity of data on analog

and digital output, which also may generate some noise in the audio signal.