Symbol

Parameter

Conditions

Min

Typ

Max

Units

PARAMETERS NOT TESTED

Capacitance at Bn

(Note 7)

5

pF

Noise Rejection

(Note 8)

1

ns

Note 6

All input risefall times should be 3 ns

Note 7

This parameter is tested using TDR techniques described in 11940 BTL Backplane Design Guide

Note 8

This parameter is tested during device characterization The measurement revealed that the part will typically reject 1 ns pulse width

Pin Description

Pin Name

Number of

Input

Description

Pins

Output

ALL1

1

O

TTLAll asserted (A logic ‘‘1’’ indicates that all the competition bits

are asserted)

8

IO

ABP

1

IO

9

NA

Parallel driver grounds reduce ground bounce due to high current

switching of driver outputs (Note 9)

ABP GND

8

IO

TTL TRI-STATEModule competition bits

CNP

1

I

TTL TRI-STATEModule competition parity bit

CMPT

1

I

TTLCompetition bit (A logic ‘‘0’’ indicates that the module will

compete in the arbitration)

GND

3

NA

Ground for switching circuits (Note 9)

CN

LE

1

I

logic states are latched with corresponding parity bit)

LI

1

NA

Power supply for live insertion Boards that require live insertion

should connect LI to the live insertion pin on the connector

(Note 10)

NC

3

NA

No connect

PER

1

O

TTLABn odd parity (A logic ‘‘0’’ indicates parity error)

AB

RE

1

I

TTLReceiver Enable (A logic ‘‘0’’ enables receivers)

QGND

1

NA

Ground for receiver input bandgap reference and non-switching

circuits (Note 9)

1NA

(Note 2)

2NA

WIN

GT

1

O

TTLWin signal (active low) During competition WIN

GT

indicates that the module has won the competition For a module

not participating in the competition WIN

GT indicates that the

module has a number which is greater than winner’s number

Note 9

The multiplicity of parallel ground paths reduces the effective inductance of bonding wires and leads which then reduces the noise caused by transients

on the ground path The various ground pins can be tied together provided that the external ground has low inductance (ie ground plane with power pins and

many signal pins connected to the backplane ground) If the external ground floats considerably during transients precautionary steps should be taken to prevent

QGND from moving with reference to the backplane ground The receiver threshold should have the same ground reference as the signal coming from the

backplane A voltage offset between their grounds will degrade the noise margin

Note 10

5