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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DS3885 датащи(PDF) 4 Page - National Semiconductor (TI) |
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DS3885 датащи(HTML) 4 Page - National Semiconductor (TI) |
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4 / 12 page  DC Electrical Characteristics (Notes 2 and 3) TA e 0 Cto a70 C VCC e 5V g10% (Continued) Note 1 Absolute Maximum Ratings are those beyond which the safety of the device cannot be guaranteed They are not meant to imply that the device should be operated at these limits The tables of ‘‘Electrical Characteristics’’ provide conditions for actual device operation Note 2 All input andor output pins shall not exceed VCC a 05V and shall not exceed the absolute maximum rating at any time including power-up and power- down This prevents the ESD structure from being damaged due to excessive currents flowing from the input andor output pins to QVCC and VCC There is a diode between each input andor output to VCC which is forward biased when incorrect sequencing is applied LI and Bn pins do not have power sequencing requirements with respect to VCC and QVCC Note 3 All currents into device pins are positive all currents out of device pins are negative All voltages are referenced to device ground unless otherwise specified All typical values are specified under these conditions VCC e 5V and TA e 25 C unless otherwise stated Note 4 Only one output should be shorted at a time and duration of the short not to exceed one second Note 5 Referenced to appropriate signal ground Do not exceed maximum power dissipation of package AC Electrical Characteristics TA e 0 Cto a70 C VCC e 5V g10% (Note 6) Symbol Parameter Conditions Min Typ Max Units DRIVER ( Figures 1 and 2 ) tPHL CN LE to AB7 Propagation Delay CMPT e 0V AB RE e 3V 7 13 18 ns tPLH 610 17 ns tr Transition TimeRiseFall AB RE e 3V CMPT e CN LE e 03 ns tf 20% to 80% AB RE e 3V CMPT e CN LE e 01 ns DRIVER TIMING REQUIREMENTS ( Figures 1 and 2 ) tS CNn to CN LE Set-Up Time AB RE e 3V CMPT e 0V 9 ns tH CN LE to CNn Hold Time AB RE e 3V CMPT e 0V 0 ns tPW CN LE Pulse Width AB RE e 3V CMPT e 0V 15 ns RECEIVER tPHL ABn to CNn Propagation Delay AB RE e 0V CMPT e CN LE e 3V 5 13 22 ns tPLH ( Figures 4 and 5 ) 315 23 ns tPLZ AB RE to CNn Disable Time CMPT e CN LE e 3V ABn e 21V 3 6 11 ns tPZL Enable Time ( Figures 6 and 7 ) 5 9 13 ns tPHZ Disable Time CMPT e CN LE e 3V ABn e 11V 4 7 12 ns tPZH Enable Time ( Figures 6 and 7 ) 3 6 11 ns OTHERS tPHL AB0 to ALL1 Propagation Delay AB k71l e 11V 7 16 28 ns tPLH All Asserted Condition ( Figures 4 and 8 ) 716 26 ns tPHL AB0 to WIN GT Propagation Delay CMPT e CN LE e 0V AB RE e 3V 6 14 23 ns tPLH Win Condition CN k70l e 0V 614 23 ns ABk70l e 21V ( Figures 4 and 9 ) tPHL AB0 to WIN GT Propagation Delay CMPT e AB RE e 3V CN LE e 0V 6 16 27 ns tPLH Greater Than Condition CN k71l e 0V CN0 e 3V 616 26 ns ABk70l e 21V ( Figures 4 and 9 ) tPHL ABP to PER Propagation Delay CMPT e CN LE e AB RE e 3V 6 13 23 ns tPLH Parity Error Condition AB k71l e 11V AB0 e 21V 413 23 ns ( Figures 4 and 8 ) tPHL ABn to AB knb1l Propagation Delay CMPT e CN LE e 0V AB RE e 3V 512 22 ns CNn e 0V CN knb1l e 3V tPLH CN k7na1l e 0V AB k7na1l e 21V 513 23 ns ( Figures 1 and 10 ) tPHL CMPT to AB7 Propagation Delay CN LE e 0V AB RE e CN7 e 3V 4 8 14 ns tPLH ( Figures 1 and 3 ) 5 9 16 ns tPHL AB7 to ABP Propagation Delay CMPT e CN LE e 0V AB RE e CNP e 3V 36 60 ns tPLH CN k70l e 0V ( Figures 1 and 10 ) 36 60 ns 4 |
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