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GND

GNDA

TESTEN

TD0−TD9

REFCLK

PRBSEN

17

22

16

SYNCEN

24

SYNC/PASS

47

10

10

RD0−RD9

2

RBC0−RBC1

ENABLE

28

TCK

49

JTMS

55

JTDI

48

JTRSTN

56

JTDO

27

LOS

26

RBCMODE

32

LOOPEN

19

MODESEL

15

Host

Protocol

Device

JTAG

Controller

VDD VDDA

2.5V

VDDPLL

GNDPLL

5 Ω at100MHz

2.5V

64

18

62

Controlled Impedance

TransmissionLine

TXP

61

ControlledImpedance

TransmissionLine

TXN

54

ControlledImpedance

TransmissionLine

RXP

52

ControlledImpedance

TransmissionLine

RXN

50 Ω

50 Ω

TLK2201A

TLK2201AI

0.01 µF

DESIGNING WITH PowerPAD™

TLK2201A

TLK2201AI

SLLS572B – JUNE 2003 – REVISED SEPTEMBER 2007

Figure 12. Typical Application Circuit (AC mode)

The TLK2201A and TLK2201AI are housed in a high performance, thermally enhanced, 64-pin VQFP (RCP64)

PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note

that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical

conductor. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly

techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD of connection etches

or vias under the package. It is strongly recommended that the PowerPAD be soldered to the thermal land. The

recommended convention, however, is to not run any etches or signal vias under the device, but to have only a

grounded thermal land as explained below. Although the actual size of the exposed die pad may vary, the

minimum size required for the keepout area for the 64-pin PFP PowerPAD package is 8 mm

× 8 mm.

Copyright © 2003–2007, Texas Instruments Incorporated

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Product Folder Link(s): TLK2201A TLK2201AI