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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP8727 датащи(PDF) 8 Page - Texas Instruments |
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LP8727 датащи(HTML) 8 Page - Texas Instruments |
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8 / 33 page  LP8727 SNVS898A – OCTOBER 2012 – REVISED MAY 2013 www.ti.com Charger Electrical Characteristics Typical values and limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the entire junction temperature range ( −40°C to +125°C). (1) (2) (3) Symbol Parameter Conditions Typ Min Max Units Over Voltage Protection Charger input is turned off if voltage is VOV 6.9 6.7 7.2 V Threshold above this threshold Over Voltage Protection VOV_HYS 170 120 220 mV Threshold Hysteresis VVBUS VBUS Operating Range 4.45 6 V VVBUS - VVBAT (Rising) 250 VOK_CHG VBUS OK Trip Point mV VVBUS - VVBAT (Falling) 40 VTERM = 4.2V, ICHG = 50 mA −0.35 +0.35 VTERM Termination Voltage VTERM is measured at 10% of the % −1 +1 programmed ICHG current Charger pass transistor ON RDSON_CHG ICHG = 400 mA 250 400 m Ω resistance 4.45V ≤ VVBUS ≤ 6V VBUS Programmable Full- VVBAT < VVBUS - VOK_VBUS 90 1100 mA Rate Charging Current VFULL_RATE < VVBAT < VTERM (4) ICHG Full-rate charging current ICHG = 400 mA −5 +5 % tolerance 2.2V < VVBAT < VFULL_RATE IPRECHG Pre-charge current 80 60 100 mA 80 mA option selected IVBUS(MAX) Maximum Input Current VVBUS - VVBAT ≤ 0.8V 2.3 A Full-rate Qualification VVBAT Rising, Transition from Pre- VFULL_RATE 2.6 2.5 2.7 V Threshold charge to Full-rate Charging End-of-charge Current, % IEOC 0.1C option selected 10 % of Full-rate Current Regulated Junction TREG 115°C option selected(5) 115 °C Temperature DETECTION AND TIMING(5) VVBUSDET VBUS Detection Threshold 3.5 3 4 V TPOK Power OK Debounce Time VVBUS > VVBAT + VOK_CHG 30 Debounce Time from Pre- ms Pre-charge to full-rate charging TPRE_FULL Charge to Full-rate 55 transition Transition Debounce Time from CV to TEOC 400 ms End-of-Charge Transition TCHG Charge Safety Timer Pre-charge Mode 45 minutes (1) Junction-to-ambient thermal resistance is highly application and board layout dependent. In applications where high power dissipation exists, special care must be given to thermal dissipation issues in board design. (2) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value. (3) The parameters in the electrical characteristic table are tested under open loop conditions at Vbat = 3.7 unless otherwise specified. For performance over the input voltage range and closed loop condition, refer to the datasheet curves. (4) The minimum input voltage equals VOUT (nom) + 0.5V or 2.5V, which ever is greater. (5) Min and Max limits are specified by design, test or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm. 8 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LP8727 |
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