LP8555 datasheet(55/64 Pages) TI1

55 / 64 page

LP8555

www.ti.com

SNVS857 – FEBRUARY 2014

11 Layout

11.1 Layout Guidelines

In Layout Example is a layout recommendation for LP8555. The figure is used for demonstrating the principle of

good layout. This layout can be adapted to the actual application layout if/where possible.

It is important that all boost components are close to the chip and the high current traces should be wide enough.

By placing one boost component on one side of the chip it is easy to keep the ground plane intact below the high

current paths. This way other chip terminals can be routed more easily without splitting the ground plane. VDD

and VLDO need to be as noise-free as possible. Place the bypass capacitors near the corresponding terminals

and ground them to as noise-free ground as possible.

Here are some main points to help the PCB layout work:

•

Current loops need to be minimized:

–

For low frequency the minimal current loop can be achieved by placing the boost components as close to

the SW and SW_GND terminals as possible. Input and output capacitor grounds need to be close to each

other to minimize current loop size.

–

Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact

under the current traces. High frequency return currents try to find route with minimum impedance, which

is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when

return current flows just under the “positive” current route in the ground plane, if the ground plane is intact

under the route. Traces from inner pads of the LP8555 need to be routed from below the part in the inner

layer so that traces do not split the ground plane under the boost traces or components.

•

GND plane needs to be intact under the high current boost traces to provide shortest possible return path and

smallest possible current loops for high frequencies.

•

Current loops when the boost switch is conducting and not conducting needs to be on the same direction in

optimal case.

•

Inductor placement should be so that the current flows in the same direction as in the current loops. Rotating

inductor 180° changes current direction.

•

Use separate power and noise free grounds. Power ground is used for boost converter return current and

noise free ground for more sensitive signals, like VDD and VLDO bypass capacitor grounding as well as

grounding the GND terminals of LP8555 itself.

•

Boost output feedback voltage to LEDs need to be taken out “after” the output capacitors, not straight from

the diode cathode.

•

A small (for example, 39 pF) bypass capacitor should be placed close to the FB terminal(s) to suppress high

frequency noise

•

VDD line should be separated from the high current supply path to the boost converter(s) to prevent high

frequency ripple affecting the chip behavior. A separate 1-µF bypass capacitor is used for the VDD terminal,

and it is grounded to noise-free ground.

•

Input and output capacitors need strong grounding (wide traces, many vias to GND plane)

•

If two output capacitors are used they need symmetrical layout to get both capacitors working ideally

•

Output capacitors DC-bias effect. If the output capacitance is too low, it can cause boost to become instable

on some loads and this increases EMI. DC bias characteristics need to be obtained from the component

manufacturer; it is not taken into account on component tolerance. X5R/X7R capacitors are recommended.

Submit Documentation Feedback

Product Folder Links: LP8555

LP8555 датащи(PDF) 55 Page - Texas Instruments

LP8555 датащи(HTML) 55 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

датащи скачать

ссылки URL