LP8551TLXSLASHNOPB datasheet(8/47 Pages) TI1

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LP8551

SNVS673E – APRIL 2010 – REVISED SEPTEMBER 2014

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7.9 Undervoltage Protection

Limits are for TA = 25°C and VIN = 12 V, VDDIO = 2.8 V, CVLDO = 1 μF, L1 = 15 μH, CIN = 10 μF, COUT = 10 μF, unless

otherwise specified. RISET = 16 kΩ

(1)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

UVLO[1:0] = 00

Disabled

UVLO[1:0] = 01, falling

2.55

2.70

2.94

UVLO[1:0] = 01, rising

2.62

2.76

3.00

VUVLO

VIN UVLO Threshold Voltage

UVLO[1:0] = 10, falling

5.11

5.40

5.68

UVLO[1:0] = 10, rising

5.38

5.70

5.98

UVLO[1:0] = 11, falling

7.75

8.10

8.45

UVLO[1:0] = 11, rising

8.36

8.73

9.20

(1)

Low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics.

7.10 Logic Interface Characteristics

Limits apply over the full operating ambient temperature range (–30°C

≤ TA ≤ 85°C), and VIN = 12 V, VDDIO = 2.8 V, CVLDO = 1

μF, L1 = 15 μH, CIN = 10 μF, COUT = 10 μF, unless otherwise specified. RISET = 16 kΩ

(1)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LOGIC INPUT EN

VIL

Input low level

0.4

VIH

Input high level

1.2

Input current

–1

μA

LOGIC INPUT PWM

VIL

Input low level

0.4

VIH

Input high level

2.2

Input current

–1

μA

LOGIC INPUTS SCL, SDA

VIL

Input low level

0.2xVDDIO

VIH

Input high level

0.8xVDDIO

Input current

μA

LOGIC OUTPUTS SDA, FAULT

VOL

Output low level

IOUT = 3 mA (pullup current)

0.3(2)

0.5

Output leakage current

VOUT = 2.8 V

–1

μA

(1)

Low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics.

(2)

Limits are TA = 25 °C.

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