LP5551 datasheet(13/38 Pages) TI1

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LP5551

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SNVS417B – DECEMBER 2006 – REVISED APRIL 2013

P-Well Characteristics

Unless otherwise noted, VDD_A, _D, VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type

apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to

+125°C

(1) (2) (3)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

VOUT

VOUT = 0 V, IOUT = 10 µA

Accuracy

Output Voltage Tolerance

2.7

≤ VDD_A, _D, PVDD1,2 ≤ 5.5 V

-0.035

0.035

Bias Current Control bits = 00

IOUT = 10 uA, VOUT = 0.3 V

Line Regulation

0.159

%/V

2.7V

≤ VDD_A, _D, PVDD1,2 ≤ 5.5 V

VDD_A, _D, PVDD1,2 = 3.6 V

Load Regulation

VOUT = 0.3 V

0.011

%/µA

0.1 uA

≤ IOUT ≤ 10 uA

VOUT Range

0 mA

≤ IOUT ≤ 10 uA

Programmable Output Voltage Offset:

Programming Resolution: See Register

-1

0.3

Referenced to Ground

Map

IOUT = 0, P-well Bias Current Control

Quiescent Current

150

270

bits = 00

ISINK

VDD_A, _D, PVDD1,2 = 3.6 V

Bias Current Control bits = 00

VOUT > VOUT(NOM) - 15 mV

(4)

VDD_A, _D, PVDD1,2 = 3.6 V

Bias Current Control bits = 01

VOUT > VOUT(NOM) - 15 mV

(4)

Output Sinking Capability

VDD_A, _D, PVDD1,2 = 3.6 V

Bias Current Control bits = 10

VOUT > VOUT(NOM) - 15 mV

(4)

VDD_A, _D, PVDD1,2 = 3.6 V

Bias Current Control bits = 11

VOUT > VOUT(NOM) - 15 mV

(4)

ISOURCE

Output Source Capability

VDD_A, _D, PVDD1,2 = 2.7 V

100

CLOAD

Output Capacitance of Load

0µA

≤ IOUT ≤ 3 uA

0.1

(1)

All voltages are with respect to the potential at the GND pin.

(2)

All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested

during production with TJ = 25C. All hot and cold limits are ensured by correlating the electrical characteristics to process and

temperature variations and applying statistical process control.

(3)

Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics

(4)

The output voltage is specified not to drop more than 15 mV (VOUT < VOUT(NOM) - 15 mV) while sinking the specified current.

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