LP3954RLSLASHNOPB datasheet(5/60 Pages) TI1

5 / 60 page

LP3954

www.ti.com

SNVS340D – JUNE 2005 – REVISED MARCH 2013

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1) (2) (3)

V (SW, FB, R1-2, G1-2, B1-2, FLASH, WLED1-6)(4) (5)

-0.3V to +7.2V

VDD1, VDD2, VDD_IO, VDDA

-0.3V to +6.0V

Voltage on ASE, IRT, IFLASH, IRGB, VREF

-0.3V to VDD1+0.3V with 6.0V max

Voltage on Logic Pins

-0.3V to VDD_IO +0.3V with 6.0V max

V(all other pins): Voltage to GND

-0.3V to 6.0V

I (VREF)

10µA

I(R1, G1, B1, R2, G2, B2)

100mA

I(FLASH)(6)

400mA

Continuous Power Dissipation(7)

Internally Limited

Junction Temperature (TJ-MAX)

150°C

Storage Temperature Range

-65°C to +150°C

Maximum Lead Temperature (Soldering) (8)

260ºC

ESD Rating, Human Body Model(9)

2kV

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits

and associated test conditions, see the Electrical Characteristics tables.

(2)

All voltages are with respect to the potential at the GND pins.

(3)

If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(4)

Battery/Charger voltage should be above 6V no more than 10% of the operational lifetime.

(5)

Voltage tolerance of LP3954 above 6.0V relies on fact that VDD1 and VDD2 (2.8V) are available (ON) at all conditions. If VDD1 and VDD2

are not available (ON) at all conditions, TI does not ensure any parameters or reliability for this device.

(6)

The total load current of the boost converter in worst-case conditions should be limited to 300mA (min. input and max. output voltage).

(7)

Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=160°C (typ.) and

disengages at TJ=140°C (typ.).

(8)

For detailed soldering specifications and information, please refer to Application Note AN1112 : Micro SMD Wafer Level Chip Scale

Package SNVA009 or Application Note AN1412 : Micro SMDxt Wafer Level Chip Scale Package SNVA131.

(9)

The Human body model is a 100pF capacitor discharged through a 1.5k

Ω resistor into each pin. The machine model is a 200pF

capacitor discharged directly into each pin. MIL-STD-883 3015.7

Operating Ratings

(1) (2)

V (SW, FB, WLED1-6, R1-2, G1-2, B1-2, FLASH)

0 to 6.0V

VDD1,2 with external LDO

2.7 to 5.5V

VDD1,2 with internal LDO

3.0 to 5.5V

VDDA

2.7 to 2.9V

VDD_IO

1.65V to VDD1

Voltage on ASE

0.1V to VDDA –0.1V

Recommended Load Current

0mA to 300mA

Junction Temperature (TJ) Range

-30°C to +125°C

Ambient Temperature (TA) Range

(3)

-30°C to +85°C

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits

and associated test conditions, see the Electrical Characteristics tables.

(2)

All voltages are with respect to the potential at the GND pins.

(3)

In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =

125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the

part/package in the application (

θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).

Thermal Properties

Junction-to-Ambient Thermal Resistance(

θJA), YZR0036AAA or YPG0036AAA Package

(1)

60°C/W

(1)

Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

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