LP3954RLSLASHNOPB datasheet(35/60 Pages) TI1

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ack from slave

msb Chip Address lsb

ack from slave

msb Register Add lsb

msb

DATA

lsb

stop

ack from slave

ack from master

repeated start

data from slave

start

Id = 54h

w ack

addr = h00

ack

r ack

Address 00h data

ack stop

msb Chip Address lsb

Id = 54h

start

SCL

SDA

start

msb Chip Address lsb

ack

msb Register Add lsb

ack

msb

DATA

lsb

ack

stop

ack from slave

SCL

SDA

start

Id = 54h

ack

addr = 02h

ack

address 02h data

stop

ADR6

Bit7

ADR5

bit6

ADR4

bit5

ADR3

bit4

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

MSB

LSB

C SLAVE address (chip address)

LP3954

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SNVS340D – JUNE 2005 – REVISED MARCH 2013

Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been

addressed must generate an acknowledge after each byte has been received.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W). The LP3954 address is 54h or 55H as selected with SI pin. For the

eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the

data will be written. The third byte contains data to write to the selected register.

Figure 39. I2C Chip Address

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = 7-bit chip address, 54h (SI=0) or 55h (SI=1) for LP3954.

Figure 40. I2C Write Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in

the Read Cycle waveform.

Figure 41. I2C Read Cycle

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