Data transfer protocol for single write operation

24

1

2

3

4

5

6

7

8

9

10

11

12

13

14

27

28

HCLK

26

25

29

1

Hdata

A7

A6

A5

A4

A3

R/W

Register Address (A7:A0)

Data In

A1

A2

D14

D13

D2

A0

D12

D1

X

D15

X

R/W

w0

D0

1 clock for next

transaction = 30

st

Hstrobe

0

T0425-01

Data transfer protocol for Read operations

16

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

27

HCLK

18

17

28

29

1

Hdata

A7

A6

A5

A4

A3

R/W

Register Address (A7:A0)

Data Out

A1

A2

D14

D13

D11

A0

D12

D10

r0

X

X

R/W

D0

D9

Hstrobe

X

D15

Hdata becomes output

Driving the line

T0427-01

THS789

www.ti.com

SLOS776A – SEPTEMBER 2012 – REVISED DECEMBER 2015

Programming (continued)

7.5.1.7 Chip ID

Address (83h) is a read-only register that identifies the product and the die revision. The 16-bit register is divided

into two 8-bit sections. The LSB represents the revision history and the MSB represents the last two digits of

THS789 device (that is, 80). The first revision (1.0) is as follows:

1000 0000 0001.0000

7.5.1.8 Read Operations

Reading the THS789 device registers via the host interface requires the following sequence:

The host controller initiates a read cycle by setting the host strobe signal, Hstrobe, to a low state. The serial

Hdata sequence starts with a high R/W bit, followed by (either 1 or 0) for parallel-write bit and 8 bits of address,

with most-significant bit (A7) first. The host controller should put the Hdata signal in the high-impedance state

beginning at the falling edge of HCLK pulse 10. The THS789 device allows one clock cycle, (r0) for the host to

reverse the data-channel direction and begins driving the Hdata line on the falling edge of HCLK pulse 11. The

data is read beginning with the most-significant bit (D15) and ending with the least-significant bit (D0).

The host must drive Hstrobe to a high state for a minimum of two HCLK periods beginning at the falling edge of

HCLK pulse 27 to indicate the completion of the read cycle. Figure 2 shows the timing diagram of the read

operation.

Figure 2. Read Operation

7.5.1.9 Write Operations

Writing into the THS789 device registers via the host interface requires the following sequence:

After the Hstrobe line is pulled low (start condition), the R/W bit is set low, followed by a 0 for the parallel-write bit

(single-register write), then the memory address (A7–A0) followed by the data (D15:D0) to be programmed. The

next clock cycle (w) is required to allow data to be latched and stored at the destination address (or addresses in

the case of a parallel write), followed by at least two dummy clock cycles during which the Hstrobe is high,

indicating the completion of the write cycle. Figure 3 and Figure 3 show timing diagrams of write operations.

Figure 3. Write Operation

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