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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TL16C552 датащи(PDF) 13 Page - Texas Instruments |
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TL16C552 датащи(HTML) 13 Page - Texas Instruments |
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13 / 33 page  TL16C552 DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PARAMETER MEASUREMENT INFORMATION Active Active Top Byte of FIFO IOR (RD LSR) CLK Sample SIN Active Time Out or Trigger Level Interrupt LSI Interrupt IOR (RD RBR) (FIFO at or above trigger level) (FIFO below trigger level) Previous Byte Read From FIFO Stop td9 (see Note A) tpd6 td9 tpd6 50 % 50 % 50 % 50 % 50 % 50 % 50 % Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms Active IOR (RD RBR) CLK Sample SIN (first byte) Stop td9 (see Note B ) RXRDY tpd7 See Note A 50 % 50 % 50 % Figure 12. Receiver Ready Mode 0 Waveforms NOTES: A. This is the reading of the last byte in the FIFO. B. When FCR0=1, then td9 = 3 RCLK cycles. For a time-out interrupt, td9 = 8 RCLK cycles. |
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